RTCC & prescaler manipulation

Kypec

Please give me anybody a straight answer to this:
Is prescaler also cleared (initialized to zero) when RTCC register
is modified (cleared or written to)?
In the datasheets I found only a statement that prescaler gets
cleared when assigned to WDT and clr !WDT opcode is executed.
According to my observations during simulation in SXSim 2.04
the prescaler is not cleared when clr RTCC is executed.
This behaviour is quite annoying to me. I'm an experienced PICmicro
developer and find it rather difficult to use RTCC for proper timing.
Consider the conditions below:
machine cycle time = 50 ns (20 MHz crystal, TURBO)
prescaler assigned to RTCC = 1:64
My routine is attempting to measure time elapsed
between two consecutive edge occurrences at pin RB0.
Wake-up pending bits testing is involved without interrupt servicing.
After the first edge is detected I zero the RTCC and wait for another edge.
However, since the prescaler is not cleared at that very moment as well,
my reading of RTCC can be misaligned by as much as 63 machine cycles

Anyway, I seem to have to live with that cause no software
can change the behaviour of silicon

Bean

I think the prescaler is cleared when you assign the OPTION register. I'm not 100% sure, but it's something to try.
Bean.

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Paul Baker

if your doing this during an interrupt routine, use retiw, otherwize try doing mov RTCC,·#0 if you have rtcc mapped to register $01

Post Edited (Paul Baker) : 2/19/2005 5:34:28 PM GMT

Guenther Daubach

Kypec,

please don't take the results achieved with SXSim for granted - especially such prescaler-related issues might not yet reflect the "real silicon".

Nevertheless, I'm glad that you came up with this question. I'll check how a "real" SX handles it, and then will adjust SXSim if necessary.

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Greetings from Germany,

G

Kypec

I'm just scanning through "Beginning Assembly Language for the SX Microcontroller".
Quotation from the Unit 7: Interrupts

page 91 said...
The subroutine sets rtcc to 1 (which also, incidentally, clears the prescaler).
It then waits for rtcc to equal zero. This will require 255 counts and each count requires 256 instruction cycles.
Therefore, at 50 MHz, the total delay is 256*255*20 ns = 1.3 ms.
Don’t forget that writing to rtcc clears the prescaler. This can lead to subtle side effects.

Anyway, I'm eagerly waiting for new SXSim release

Kypec

Bean

I thought of that after my previous post. The precaler doesn't get cleared when you assign OPTION, it gets cleared when you assign RTCC.

Bean.

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