Stamp architecture

Newzed

Are ALL Stamps TTL compatible?· No CMOS inouts or outputs?

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Sid Weaver
Do you have a Stamp Tester?

http://hometown.aol.com/newzed/index.html
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MacGeek117

Yes, but I've connected CMOS chips to a Stamp.
bugg

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I think I know what I'm doing...

Newzed

Bugg, I', driving the Stamp with a device that has a max of 3.0VDC output on the SO and SI lines.· Just wanted to·make sure I was OK, which apparently I am.

Thanks

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Sid Weaver
Do you have a Stamp Tester?

http://hometown.aol.com/newzed/index.html
·

MacGeek117

I'm pretty sure all the Stamps are TTL.
bugg
Please correct me if I'm wrong.

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I think I know what I'm doing...

Jim McCorison

Sid,

The only potential problem that I see is that the TTL logic levels in the stamp define anything above 1.6 vdc as a true. This gives you only 1.4vdc max of headroom between a true and false condition. Too much voltage drop or noise in the circuit could cause an incorrect reading.

Jim

Newzed

I don't think headroom is a problem, Jim.· I think I put my scope on it a couple of days ago and it was dropping to almost 0.· My real concern was that the 3 volt max output was enough to drive the Stamp to a true.· The unit still is not working right, so tomorrow I'll put the scope on the output line from the device and see what I get.

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Sid Weaver
Do you have a Stamp Tester?

http://hometown.aol.com/newzed/index.html
·

Paul Baker

the headroom hes talking about is Vih (minimum voltage to register as logic level high) to Vdd, Vih is 1.6V for TTL, running at 3V yeilds 1.4V margin. CMOS will adjust its Vil and Vih according to Vdd but TTL doesn't.