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DEC W and RL W instructions — Parallax Forums

DEC W and RL W instructions

Tony LeylandTony Leyland Posts: 71
edited 2005-02-07 22:42 in General Discussion
Hi,

Does anybody know why, when the DEC W and RL W instructions are used, the Assembler
generates DEC IND and RL IND instructions respectively ?

Thanks in advance,

Tony Leyland

Comments

  • Guenther DaubachGuenther Daubach Posts: 1,321
    edited 2005-02-04 15:39
    Tony,

    I deleted my other post concerning your question because it contained a wrong explanation, or - IOW - complete nonsense smile.gif .

    Actually, the SX does not support DEC W and RL W instructions. These (and some other) instruction can only be applied to file registers but not to the W register. I must admit that I made similar mistakes more than once, and later was wondering what happened to some register contents.

    Maybe, Peter could at least let SASM generate a warning when DEC, INC, RL, RR instructions are applied to the W register.

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    Greetings from Germany,

    G
  • Tony LeylandTony Leyland Posts: 71
    edited 2005-02-04 15:49
    Hi G
  • BeanBean Posts: 8,129
    edited 2005-02-04 16:00
    I believe those instructions should be assembling as "DEC 01" and "RL 01" instead of "DEC 00" and "RL 00" because you can set location 01 to be the "W" register by setting the option bit.

    Bean.
  • James NewtonJames Newton Posts: 329
    edited 2005-02-05 00:34
    Hang on there guys. The SX CAN DEC W and RL W, but only if the option register is set to allow that. Bit 7 (the 8th bit) of OPTION is called RTW. If RTW is 0 then register 1 is W but if RTW is 1 then register 1 is the RTCC. Register 0 is always IND so I have no idea why the compiler would be generating commands that target that register.

    At first I thought that perhaps something in your program must have assigned the value 0 to the symbol W, but W is reserved and as this little test program listing shows, SASM thinks the value of W is 0.
         4  0001  00E0          dec W
         5  0002  00E0          dec ind
         6  0003  00E1          dec rtcc
         7  =00000000           what = w
    Cross Reference
    7 symbols
    Symbol                            Type   Value      Line
    __SASM                            DATA   00000001   0000
    __SX_FREQ                         DATA   02FAF080   0008
    __SX_IRC_CAL                      DATA   00000000   0008
    ind                               RESV   00000000   0005
    rtcc                              RESV   00000001   0006
    W                                 RESV   00000000   0004
    what                               VAR   00000000   0007
    

    SASM should have compiled dec W to 00E1 just like dec rtcc. I think this is a compiler bug. Peter! Oh Peter! <GRIN>

    I've actually spent some time looking at the instruction set and I don't see any reason why W should be assigned to 0. It doesn't "help" the compiler for other instuctions to have W at a value of 0. To see what I mean, if the compiled value of CLR W was the same as the compiled value of CLR FSR (for example) except that the bits that are set to 4 to indicate FSR were instead set to 0 to indicate W then it would make sense. But the actual compiled value for CLR W and CLR fr are totally different.

    For more on the opcodes see:

    http://www.sxlist.com/opcodes

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    ---
    James Newton, Host of SXList.com
    james@sxlist.com 1-619-652-0593 fax:1-208-279-8767
    SX FAQ / Code / Tutorials / Documentation:
    http://www.sxlist.com Pick faster!



    Post Edited (James Newton) : 2/5/2005 1:00:42 AM GMT
  • Guenther DaubachGuenther Daubach Posts: 1,321
    edited 2005-02-05 01:06
    James,

    according to the "official" Ubicom SX docs, it's not the case that the SX can DEC W, or RL W, etc. Bit 7 in OPTION only controls which register (RTCC or WREG) should be mapped to location 1 in the global registers section.

    I did some experiments with SK-Key, and I can confirm that DEC W, RL W, etc. instructions always touch the register indiretly addressed by FSR, independently of the OPTION.7 setting.

    This confirms my understanding of the "official" Ubicom SX docs, i.e. OPTION.7 only controls the mapping of RTCC or W to location 1, IOW, if OPTION.7 = 1 (the default), any access to location 1 will read/modify the RTCC or, when OPTION.7 = 0 accesses to location 1 will read/modify the WREG. I have verified this by single-stepping some test code with the SX-Key.

    As a matter of fact, I wanted to figure out what happens when the RTCC is "outmapped" (i.e. OPTION.7 = 0) and an application makes use of RTCC roll-over interrupts. Keep cool - it still seems to work fine (at least according to the results that SX-Key delivers).

    Bean,

    I don't agree with you that such instructions should be assembled to "DEC 01" and "RL 01" instead of "DEC 00" and "RL 00" as this can cause another pitfall depending on the setting of OPTION.7 - therefore, I still vote for a warning issued by SASM when DEC W, RL W, etc. instructions are found in the code.

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    Greetings from Germany,

    G
  • James NewtonJames Newton Posts: 329
    edited 2005-02-05 01:21
    Guenther,

    if OPTION.7 = 0 then dec W is a perfectly valid instruction IF it compiles to E1. W will be decremented.

    dec W should compile to DEC 01 if OPTION.7 = 0 and should issue a warning if OPTION.7 = 1.

    Of course it is very difficult for SASM to know what OPTION is going to be between run time and compile time so I vote for a warning that can be ignored.

    BTW I looked back into some of my very old code and in the SXKey compiler, any use of W generated a full stop error so I had defined WReg = 1 and would do dec WReg when I had OPTION.7 cleared.

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    ---
    James Newton, Host of SXList.com
    james@sxlist.com 1-619-652-0593 fax:1-208-279-8767
    SX FAQ / Code / Tutorials / Documentation:
    http://www.sxlist.com Pick faster!



  • BeanBean Posts: 8,129
    edited 2005-02-05 03:16
    Right James,
    DEC W should assemble to DEC 01, but still give a warning like Guenther wants.
    For DEC W to assemble to DEC 00 is no use what so ever.

    I could have sworn in an earlier version that DEC W DID assembly to DEC 01 ???

    Bean.
  • BeanBean Posts: 8,129
    edited 2005-02-05 03:20
    I discovered something...
    If you use "DEC WREG" then it DOES assemble as "DEC 01" as it should.

    So it seems you have to use "WREG" instead of just "W"

    Bean.
  • Guenther DaubachGuenther Daubach Posts: 1,321
    edited 2005-02-05 09:04
    James and Bean,

    you have convinced me. Under the condition that OPTION.7 is clear, DEC 1 actually decrements W, etc. But as James mentioned, the Assembler cannot determine if OPTION.7 is clear or not as this setting might happen in some subroutine, or somewhere else in the code.

    Therefore, I'm with Bean - DEC W should assemble to DEC 01 instead to DEC 00 with an appropriate warning.

    Bean: What a discovery - I never tried "WREG" instead of "W" as I was too lazy writing four letters instead of just one. Seems as if this is really a bug in SASM. Peter, are you with us???

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Greetings from Germany,

    G
  • PJMontyPJMonty Posts: 983
    edited 2005-02-05 18:58
    Yeah, I'm here. I was just waiting for the smoke to clear and the dust to settle before I poked my head in. As someone else pointed out, it's hard (I'd say impossible) to know which mode the code will run OPTION.7 in. I say impossible since the code could change it more than once in a program. Why would someone do this? I have no idea, but I have long since given up on trusting that people will ever do "normal" things with a CPU. I always assume that any legal code will be tried by someone somewhere, and try and make sure any changes I make take this into account.

    Anyway, changing the default value of "W" from 0 to 1 is easy. Adding a warning to a specific instruction followed by a specific value is a lot more work. I'll have to look into what is involved with adding this warning. I'm not saying that it's not worth doing the work, I'm just saying that the way SASM was designed, some things are harder to implement than you might think.
      Thanks, PeterM
  • BeanBean Posts: 8,129
    edited 2005-02-05 23:36
    Amen brother...
    Bean.
  • Guenther DaubachGuenther Daubach Posts: 1,321
    edited 2005-02-05 23:39
    Peter,

    yes, I'm completely with you - adding a warning to a specific instruction followed by a specific value is not a walk through the park. On the other hand, you already managed to generate a warning when one of the skip instructions is followed by multi-byte instruction (one of the most important enhancements of SASM, IMO). So I'm pretty sure, you are capable of doing this one. Nevertheless, it would at least make a lot sense to change the default value of "W" from 0 to 1 to make it consistent to "WREG".

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Greetings from Germany,

    G
  • James NewtonJames Newton Posts: 329
    edited 2005-02-06 23:47
    Most of my code has OPTION.7=0 in the main code and changes OPTION.7=1 in the ISR. The ISR changes it back to 0 before returning.

    Manipulating W as if it were a file register in the main code can save a cycle or two and makes life easier for the programmer.

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    ---
    James Newton, Host of SXList.com
    james@sxlist.com 1-619-652-0593 fax:1-208-279-8767
    SX FAQ / Code / Tutorials / Documentation:
    http://www.sxlist.com Pick faster!



  • PJMontyPJMonty Posts: 983
    edited 2005-02-07 22:42
    James,

    Of course. Who else should I have thought of when it came to finding someone who does "interesting" things with his source code. You need help, my friend. Lots of deep, psychological help...
      Thanks, PeterM
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