EMI and the SX52
Paul Baker
Posts: 6,351
I was reading through the EMI literature for the SX52 (http://www.parallax.com/dl/appnt/sx/An34Sx52Emii.pdf)
and came across this passage:
4.2 Reducing the Power and Ground Loop Area
The long supply lines with the relatively large areas that these lines surround may form an effective antenna. At the frequencies present, an unacceptable level of interference may be radiated. A grounded area under the SX device must be connected to the Vss pin. In addition, the ground area should be tied to the ground plain with multiple vias. This ground area ensures that the major part of the field lines emanating from the SX are concentrated between the SX and the ground level.
Does this mean it is suggested that we place a ground plane on the same side as the SX52 (fitting within the solder pads) and connect it to the ground plane on the other side of the board through vias? Is routing signals directly underneath the chip a frowned upon practice? I am commiting my design to PCB and wish to avoid any issues (especially in the black art of EMI), since this is the first time I'll be pcb'ing a system running at this frequency.
Paul
for a photographic explanation of what I'm talking about look at figure 4.3 (pg 9) of this document: http://www.sparkfun.com/datasheets/IC/CP2101Rev1_5.pdf·the center landing connected to the ground pin through the hatched gray area, and vias in this rectange connecting it to a ground plane the other side of the pcb
Post Edited (Paul Baker) : 1/22/2005 9:06:23 PM GMT
and came across this passage:
4.2 Reducing the Power and Ground Loop Area
The long supply lines with the relatively large areas that these lines surround may form an effective antenna. At the frequencies present, an unacceptable level of interference may be radiated. A grounded area under the SX device must be connected to the Vss pin. In addition, the ground area should be tied to the ground plain with multiple vias. This ground area ensures that the major part of the field lines emanating from the SX are concentrated between the SX and the ground level.
Does this mean it is suggested that we place a ground plane on the same side as the SX52 (fitting within the solder pads) and connect it to the ground plane on the other side of the board through vias? Is routing signals directly underneath the chip a frowned upon practice? I am commiting my design to PCB and wish to avoid any issues (especially in the black art of EMI), since this is the first time I'll be pcb'ing a system running at this frequency.
Paul
for a photographic explanation of what I'm talking about look at figure 4.3 (pg 9) of this document: http://www.sparkfun.com/datasheets/IC/CP2101Rev1_5.pdf·the center landing connected to the ground pin through the hatched gray area, and vias in this rectange connecting it to a ground plane the other side of the pcb
Post Edited (Paul Baker) : 1/22/2005 9:06:23 PM GMT
Comments
I would say that try to route your sensor paths away from paths that would contain some AC/noise.· Certainly don't route them parallel to them if you don't have to....they say if you must cross paths, do it at a 90deg angle.
It really depends on how 'tight' your design is supposed to be....are you measure .Nths of volts on an A/D? then yes you'd definately want to have a 'quiet' board.· Also, you'd want to 'couple' any inputs and outputs on to your board.· Again, dependson how tight you want it!
the via's they are talking about are throughboard interconnections (little holes in the board that go to a trace on the other side; they're usually filled with solder for electrical conneciton)....
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Steve
http://members.rogers.com/steve.brady
"Inside each and every one of us is our one, true authentic swing. Something we was born with. Something that's ours and ours alone. Something that can't be learned... something that's got to be remembered."
Like you, this is my first time using a SX52 and the third time I've used ExpressPCB to make my boards. I used the 52 Con Carne
as a proto type on a bread board and I had no noise problem, so on my circuit I modeled the area around the SX52 similar to the layout of the 52 Con Carne. Prior to designing the board, I also read the article you mention. It's got some good points to follow ; however, that evaluation board they used to test the SX52 is no longer around, so I'm not sure of the layout of ground planes, traces, etc.
My circuit operates at 20mhz and uses no analog signals so that unto itself lends it to a more robust environment. The 52 Con Carne
has one ground plane on the bottom layer that pretty much has the same profile as the chip except for a few spots on the edges where vias are used to bring some pins down and out to the DIP pins. I think because of the nature (SMT to DIP) of the Con Carne, the traces radiate out from the chip, there's no need to pass under the chip on the top layer.
Obviously, I can't see what's going on on the top layer below the SX52, but it's apparent that the Vdd and the Vss traces come in to the chip as two lines with one by-pass capacitor. The Vdd and Vss traces then branch out on the top layer under the chip connecting all the Vss and Vdd pins respectively. I did my board likewise; the Vss and Vdd pins all respectively connect on the top layer beneath the chip and my by pass capacitor (0.1 mf tantalum, not SMT) is mounted on the opposite side of the chip with the leads that poke out towards the chip cut flush so that they don't protrude. The open real estate is filled in with ground planes on top and bottom and inter connected with vias. I have 5 other digital chips on the miniboard (3.8"x2.5") all with their own by pass capacitors plus a couple of caps on the 7805 voltage regulator. All in all, the Con Carne PCB isn't that elaborate, one by pass cap and a small ground plane. With it's long leads and stuck into a proto board with it's associated noisy environment it worked well.
As far as passing signal traces under the chip, I have one that loops from one pin to a pin further down the same side of the chip. I needed the MIWU capability of a pin on port B but needed to read in the complete byte on port c, hence the splitting of an input signal to 2 pins. I don't anticipate any false signals due to any noise, but that remains to be seen. My boards are expected to arrive on wednesday. I hope this helps but I can't be any more scientific... my "semi-anechoic chamber" happens to be the corner of my garage where I have my electromnics bench.
later, Kevin
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There are 10 kinds of people in the world.... those that know binary, and those that don't.
Paul
This is the backside. Pin 1 is in the upper right, The left most bigger trace on the top is Vdd. the next small trace to the right of that is MCLR. The 2 traces on the right side ( next to the single via connected to the ground plane) are OSC2 and OSC1 from top to bottom. The 3 traces on the right below those are RA0, RA1,RA2.
later, Kevin
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There are 10 kinds of people in the world.... those that know binary, and those that don't.
··· A very interesting topic indeed.· As we·design boards·for the SX, we try stick to these guidlines:
1)· All four SX48/52·VSS connections connected to a ground plane.
2)· All four SX48/52 VDD connections connected to a power plane or fat supply line >30mil wide for 1/2 oz Cu.
3)· SX chip should be located as close as possible to the power source.· The oscillator/crystal/resonator should be located as close as possible to the SX chip.
4)· Power connection traces, both VSS and VDD, should be short and fat.
5)··Place a decoupling cap (o.1uF or so), at each VDD pin.
6)· The smaller the via that you use, the more of them you should use when you connect something down to the ground plane.· Larger vias are better.
7)· Flood ground liberally and use many vias to connect to ground planes on other layers.
8)· Try to flood ground around high-impedence circuits.· This practice can help cut cross-talk and noise on sensitive lines.
If you have a design that you would like to have reviewed, you are welcome to send it to me for comment.· Just use the contact info below to send a JPG, BMP, or·a PDF of your layout if you are interested.
John Barrowman
Engineering
Parallax, Inc.
www.parallax.com
jbarrowman@parallax.com
·
Paul
P.S. I have noticed a greater number of Parallax employees participating in the forums and I am thankful and appreciative for it.
Post Edited (Paul Baker) : 1/25/2005 2:50:27 AM GMT
I like to flood ground where ever I can. However, considering the SX's pin-out, I typically flood a VDD plane beneath the SX chip on the top layer and connect it with several vias to a really fat supply trace on the bottom layer. This helps afford room for decoupling caps on the top layer at each VDD pin. With ground flooded liberally on the bottom layer, it is then easy to plant vias near each VSS pin.
If you are more concerned with dissipating the heat of the SX chip you can flood ground below the SX chip on the top layer and use plenty of vias to connect it to the ground plane on the bottom layer.
A ground plane is no substitute for a heat-sink, but in some circumstnces may make the difference between using a heat-sink or not.
John B.
Paul
Post Edited (Paul Baker) : 1/25/2005 6:23:07 PM GMT
Low ESR caps are a good idea for 50M+ operation. When you stuff the board for the first time, check the VDD rail for oscillation. Fine print: some regulators cannot handle low ESR caps on their output and may oscillate, so test it before you put it in concrete.
John B.
It says it has an EMI filter, will this help the regulator from oscillation due to low ESR caps or is this just to prevent EMI injection from/to the AC power?
That power supply should do fine. Don't worry about oscillations. The EMI filter will prevent high-frequency noise from propagating in both directions. Go ahead and use low-ESR caps to decouple the SX.
John B.
-Paul