A Fast Data Aquisition System

Paul Baker

I am contemplating creating an extremely fast data acquisition system, I have a 128KB asynchronous SRAM with a 12ns access time. Using·only an·SX, I've figured the quickest code to pump the SRAM full of information (for 64KB of the SRAM)·is:
·
:loop··setb ra.0
······ clrb·ra.0
······ inc rb
·······snz
······· inc rc
······ jmp :loop
·
Where ra.0 is the write strobe to the SRAM, and rb and rc are the address. Termination of the loop is accomplished via the RTCC overflow via the RTCC pin by a user signal.·Each iteration of the·loop is 8 cycles which results in a 5.55 MHz rate of acquisition. By using a couple external counters (74F256 if I remember correctly) and driving the counter by the write signal (some delay via·an inverter to provide the SRAM with enough address hold time would also be necessary), I can reduce the loop to:
·
:loop· setb ra.0
······ clrb ra.0
·······jmp :loop
·
Each loop iteration is 5 cycles producing an acquisition rate of 10MHz. Fast, but I want even faster. The jump is now the limiting factor, but I can't unroll the loop without introducing a lack of symmetry into the acquisition. So I have come up with the following solution: the ra.0 pin is attached to a serial delay line with 5 taps having a start to finish delay of 100ns (available from Dallas·Semiconductor), feed the 5 taps + ra.0·to a 8->4 priority encoder, feed the encoded value to a parity generator chip, feed the output of the parity generator chip to the external counter and SRAM. To show you how this works the loop code must be be changed to:
·
:loop· clrb ra.0
······ setb rb.0
······ nop
······ jmp :loop
·
The clear and set of the strobe are reversed, since the priority encoder is an active low signal.·A mapping of the data is:
·
Cycle 1,······ Cycle 2,····· Cycle 3,····· Cycle 4,····· Cycle 5,····· Cycle 6
0············· 1············ 1············ 1············ 1············ 1
1············· 0············ 1·············1············ 1············ 1
1 -> $0 -> 0·· 1 -> $1 -> 1· 0 -> $2 -> 0· 1 -> $3 -> 1··1 -> $4 -> 0· 1 -> $5 -> 1
1············· 1············ 1·············0············ 1············ 1
1············· 1············ 1············ 1············ 0············ 1
1············· 1············ 1·············1············ 1············ 0
·
The nop is inserted to align the system so there is an alternation of bits between each cycle, the first column is the ra.0 bit followed by the output of each of the delay outputs, the 2nd number (the hex value) is the output of the priority encoder and the final result is the odd parity output of the parity generator (the even parity output would work too). This method would yield a 25MHz data acquisition system since clocking signals would be produced even when a jump is occurring within the SX.·My question is: is there a simpler/more elegant solution? could I perhaps connect a clock buffer circuit (with an enable pin) to the resonator of the SX or would that effect the ability of the resonator driving of the SX (maybe use the resonator to drive a fan out (of 2 or more) clock buffer to drive the SX off one output and the SRAM system off another?·
·
Paul

Bean

Paul,
Just something to watch out for. I don't think you can toggle a bit in consecutive instructions because of how the instructions are executed in the pipeline. Or maybe that only applies to reading the pin ???

Bean.

Paul Baker

Thanks for the heads up, but I think that pertains to RMW (read-modify-write) where 2 RMW are in succession. Someone correct if I'm wrong please.

Post Edited (Paul Baker) : 11/16/2004 9:41:57 PM GMT

Jim Brain

If you are going to add 2 counters to deal with the address line, why not just do this.

Get a 75 MHz oscillator.· Run the SX off of it, and add a 74F00 into your idea.· Tie one of the NAND inputs to the oscillator, the other to a pin on the SX.· Tie the output to the enable lines on the counters, and feed the 75MHz into the counters as well.· Feed the carry out of the high counter to an INT of the SX and also add it into the line to stop the clock when it goes hi

Then, you simply strobe the pin to start acq, and it will INT you when it is done.· 75MHz data acq as well.

Jim

Paul Baker

Jim, interesting twist, it hadn't occurred to me to make the counter free running (well·it did sorta at the end of my first post, but a·0 cycle overhead is·very cool). I have searched for 75 MHz clock generators (resonators, oscillators, etc) and I am unable to find a supplier who will sell them in small quantities (It would be fabulous if Parallax would use its buying power in order to make them available to the little guy). While the SRAM is rated at 12ns, I'll have to check the specs to see if that is the access time or the cycle time (if it is the access time, I may not be able to run it at 75MHz due to address setup and address hold requirements). I am a little leery of tapping directly into the signal driving the SX, my understanding is that as the clock speed increases, the deleterious affects from parasitic capacitance and inductance (caused by the pin and the input gate of the transistor of the 74F00) can cause havoc on an oscillator. Not having access to an oscilloscope, I would not be able to troubleshoot the system in the event of any problems.

As an aside, anyone have an idea for a programmable data acquisition rate? My guess is a divide by N counter.

Paul

Post Edited (Paul Baker) : 11/17/2004 3:27:31 PM GMT