Digest Number 2287
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Posts: 46,084
Hi Mark,
I'm the one who sent the example code.
Let's look at a piece of it and I'll see if I can help make it make sense.
You MUST have the STAMP and LS7166 wired as follows or modify
the code to match your wiring. For testing sake, I suggest wire as in
my example and get that working first.
'The example is based on wiring as follows:
'Stamp pin ls7166 pin
'P0/P7 D0/D7
'P8 CS
'P9 WR
'P10 RD
'P11 C/D
'Connect ls7166 pins 3 and 4 to 5volts (disable)
'
Code
example
ENC_COUNT VAR Word ' WORD to hold encoder count ls bytes
ENC_COUNTHI VAR Byte 'BYTE to hold encoder count ms byte
'Set initial STAMP2 I/O conditions
DIRS = $0F00 'I/O pins 0-7=IN, 8-11=OUT
OUTC = $F 'LS7166 CD=1, WR=1, RD=1, CS=1 (0 true)
'Setup LS7166 initial conditions
RESET:
DIRL = $FF 'bus = output
'Set OCCR count control register
OUTL = $80 'count normal binary
OUTC = $C 'CD=1, RD=1, WR=0, CS=0
OUTC = $F 'CD=1, RD=1, WR=1, CS=1
'
The 8 I/O bits are on P0 thru P7, so OUTL can be used to change
all 8 lines at once. This is the "data bus".
The next 4 I/O pins are P8 thru P11 and may be controlled simultaneously
using OUTC. These are the CS(chip select), WR(write), RD(read), and
CD(control/data)
signals for the 7166. The 7166 is pretty forgiving timing wise and MOST
things
actually take place when the CS signal transitions from true(0) to false(1).
So, at RESET we see DIRL = $FF. This sets the bus bits all to output mode
because we are sending data TO the 7166.
During setting initial Stamp I/O conditions the 4 control bits were all set
to
1(false) or OFF with OUTC = $F
Now we use OUTL = $80 to set the state of the bus data lines to the 7166.
The 7166 registers are addressed by the 2 most significant bits on the data
bus, in this case 10 = the "Output Control Register". The remaining bits are
all zero. Bit 0=0 selects binary count mode for the internal 7166 counter.
Bit 1=0 always should be 0. Bit 2=0 selects normal wrap around count mode.
Bit 3=0 always should be 0. Bits 4 and 5=0 work together to define the
function of 7166 pins 16 and 17. I wasn't using them in the example so I just
defaulted to pin16=carry low true, pin17 borrow low true.
Now we have to tell the 7166 to write the data on the bus to the register.
Here OUTC = $C 'CD=1, RD=1, WR=0, CS=0 sets WR and CS true(0), and
CD=1 says "control mode" and RD=1 says we are NOT reading.
OUTC = $F 'CD=1, RD=1, WR=1, CS=1 sets WR and CS false(1) with no
change in CD and RD (they are both always 1 in this case).
Toggling both WR and CS bits together is fine with the 7166. It actually is
looking for the low to hi transition on the WR line. The USDigital book
says to hold the data bus, chip select, and Control/Data lines stable at
least
50 nanoseconds after deasserting WR, but I have not found it to be that
particular.
Hope this helps you understand whats going on in my example.
Dennis
In a message dated 2/19/04 8:29:47 AM Central Standard Time,
basicstamps@yahoogroups.com writes:
> From: "lakewood5982003" <598@m...>
> Subject: another ls7166 question
>
> hi guys, i want to thank the responer to my last question who
> supplied some start up code. i tried the code but it didn't work, i
> think it was meant as an example only, so i am know delving deeper
> inot getting this chip to work. i am looking through the data sheet
> for this chip and it appeares that the cs pin and the wr pin are
> pulsed low for access to one of the 4 registers, my my question is
> how can the stamp output from say OUTC and pulseout a pin
> simultanesly?
>
> amrk
[noparse][[/noparse]Non-text portions of this message have been removed]
I'm the one who sent the example code.
Let's look at a piece of it and I'll see if I can help make it make sense.
You MUST have the STAMP and LS7166 wired as follows or modify
the code to match your wiring. For testing sake, I suggest wire as in
my example and get that working first.
'The example is based on wiring as follows:
'Stamp pin ls7166 pin
'P0/P7 D0/D7
'P8 CS
'P9 WR
'P10 RD
'P11 C/D
'Connect ls7166 pins 3 and 4 to 5volts (disable)
'
Code
example
ENC_COUNT VAR Word ' WORD to hold encoder count ls bytes
ENC_COUNTHI VAR Byte 'BYTE to hold encoder count ms byte
'Set initial STAMP2 I/O conditions
DIRS = $0F00 'I/O pins 0-7=IN, 8-11=OUT
OUTC = $F 'LS7166 CD=1, WR=1, RD=1, CS=1 (0 true)
'Setup LS7166 initial conditions
RESET:
DIRL = $FF 'bus = output
'Set OCCR count control register
OUTL = $80 'count normal binary
OUTC = $C 'CD=1, RD=1, WR=0, CS=0
OUTC = $F 'CD=1, RD=1, WR=1, CS=1
'
The 8 I/O bits are on P0 thru P7, so OUTL can be used to change
all 8 lines at once. This is the "data bus".
The next 4 I/O pins are P8 thru P11 and may be controlled simultaneously
using OUTC. These are the CS(chip select), WR(write), RD(read), and
CD(control/data)
signals for the 7166. The 7166 is pretty forgiving timing wise and MOST
things
actually take place when the CS signal transitions from true(0) to false(1).
So, at RESET we see DIRL = $FF. This sets the bus bits all to output mode
because we are sending data TO the 7166.
During setting initial Stamp I/O conditions the 4 control bits were all set
to
1(false) or OFF with OUTC = $F
Now we use OUTL = $80 to set the state of the bus data lines to the 7166.
The 7166 registers are addressed by the 2 most significant bits on the data
bus, in this case 10 = the "Output Control Register". The remaining bits are
all zero. Bit 0=0 selects binary count mode for the internal 7166 counter.
Bit 1=0 always should be 0. Bit 2=0 selects normal wrap around count mode.
Bit 3=0 always should be 0. Bits 4 and 5=0 work together to define the
function of 7166 pins 16 and 17. I wasn't using them in the example so I just
defaulted to pin16=carry low true, pin17 borrow low true.
Now we have to tell the 7166 to write the data on the bus to the register.
Here OUTC = $C 'CD=1, RD=1, WR=0, CS=0 sets WR and CS true(0), and
CD=1 says "control mode" and RD=1 says we are NOT reading.
OUTC = $F 'CD=1, RD=1, WR=1, CS=1 sets WR and CS false(1) with no
change in CD and RD (they are both always 1 in this case).
Toggling both WR and CS bits together is fine with the 7166. It actually is
looking for the low to hi transition on the WR line. The USDigital book
says to hold the data bus, chip select, and Control/Data lines stable at
least
50 nanoseconds after deasserting WR, but I have not found it to be that
particular.
Hope this helps you understand whats going on in my example.
Dennis
In a message dated 2/19/04 8:29:47 AM Central Standard Time,
basicstamps@yahoogroups.com writes:
> From: "lakewood5982003" <598@m...>
> Subject: another ls7166 question
>
> hi guys, i want to thank the responer to my last question who
> supplied some start up code. i tried the code but it didn't work, i
> think it was meant as an example only, so i am know delving deeper
> inot getting this chip to work. i am looking through the data sheet
> for this chip and it appeares that the cs pin and the wr pin are
> pulsed low for access to one of the 4 registers, my my question is
> how can the stamp output from say OUTC and pulseout a pin
> simultanesly?
>
> amrk
[noparse][[/noparse]Non-text portions of this message have been removed]