SV: [basicstamps] connecting RAM to bs2p
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Posts: 46,084
Greetings!
One way to do it would be to connect the 8 Data and Chip Select/Enable pins
to IO pins on the BS2, then use counter chips connected to the address
lines. (Driven by another IO pin)
A classic example of this technique is here:
http://home.c2i.net/trygveh/english/gadgetman/pocket/psion/org1pak.html
Here a 8KB EPROM is accessed in this way.
Later packs uses other counters, or even two separately clocked counters for
'paged' addressing.
(Faster than a 'flat' address and one counter)
:-)
Trygve
Opprinnelig melding
Fra: d0gbertthegreat [noparse]/noparse]mailto:[url=http://forums.parallaxinc.com/group/basicstamps/post?postID=4Qn2a4jj4qwgIGEAcvWg5QR921rKFYCyL2i5R-zBGxyL5v25eifsqVtqsFnHEQwkkBWvv1_obFDejnrYW68hLFBE]d0gbertthegreat@y...[/url
Sendt: 2. april 2003 04:08
Til: basicstamps@yahoogroups.com
Emne: [noparse][[/noparse]basicstamps] connecting RAM to bs2p
I've been coming up with plans to let a bs2p access a parallel 32K
SRAM chip but none of them seem feasible. Does anyone have a
schematic or at least an idea how to do this without it being to
complex? I'm not a very good wirer or adept at soldering.
thanx
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One way to do it would be to connect the 8 Data and Chip Select/Enable pins
to IO pins on the BS2, then use counter chips connected to the address
lines. (Driven by another IO pin)
A classic example of this technique is here:
http://home.c2i.net/trygveh/english/gadgetman/pocket/psion/org1pak.html
Here a 8KB EPROM is accessed in this way.
Later packs uses other counters, or even two separately clocked counters for
'paged' addressing.
(Faster than a 'flat' address and one counter)
:-)
Trygve
Opprinnelig melding
Fra: d0gbertthegreat [noparse]/noparse]mailto:[url=http://forums.parallaxinc.com/group/basicstamps/post?postID=4Qn2a4jj4qwgIGEAcvWg5QR921rKFYCyL2i5R-zBGxyL5v25eifsqVtqsFnHEQwkkBWvv1_obFDejnrYW68hLFBE]d0gbertthegreat@y...[/url
Sendt: 2. april 2003 04:08
Til: basicstamps@yahoogroups.com
Emne: [noparse][[/noparse]basicstamps] connecting RAM to bs2p
I've been coming up with plans to let a bs2p access a parallel 32K
SRAM chip but none of them seem feasible. Does anyone have a
schematic or at least an idea how to do this without it being to
complex? I'm not a very good wirer or adept at soldering.
thanx
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