How to stop HIGH pin from toggling

Archiver

I read somewhere how you could stop the repeated cycling of a pin,
which when held in a HIGH state is set to LOW for a very short
duration, as the BS2 does its housekeeping. When I set one of the
pins HIGH, it must stay in that state, without a single glitch,
until told to go low. This pin is actually supplying the bias
voltage to the input transistor in an oscillator stage, so a
momentary interruption of that voltage is going to play havoc with
the oscillators.

Is there a way to wire up a filter circuit, or maybe just a cap or
two, that would effectively isolate a downstream component from the
intermittent "toggles"?

thanks, and I hope you know what I am talking about !!8-)

Jim D. Martin

Archiver

If what you're experiencing is the Stamp Watchdog Timer (used during certain
low-power modes), a possible solution would be to pull the pin high through
a pull-up resistor (e.g. 10K). Then the Stamp can pull that pin low as
required to turn off the oscillator.

-- Jon Williams
-- Parallax


In a message dated 11/1/01 5:53:06 PM Central Standard Time,
jimdmartin@a... writes:


> I read somewhere how you could stop the repeated cycling of a pin,
> which when held in a HIGH state is set to LOW for a very short
> duration, as the BS2 does its housekeeping. When I set one of the
> pins HIGH, it must stay in that state, without a single glitch,
> until told to go low. This pin is actually supplying the bias
> voltage to the input transistor in an oscillator stage, so a
> momentary interruption of that voltage is going to play havoc with
> the oscillators.
>
> Is there a way to wire up a filter circuit, or maybe just a cap or
> two, that would effectively isolate a downstream component from the
> intermittent "toggles"?
>
> thanks,




[noparse][[/noparse]Non-text portions of this message have been removed]

Archiver

>I read somewhere how you could stop the repeated cycling of a pin,
>which when held in a HIGH state is set to LOW for a very short
>duration, as the BS2 does its housekeeping. When I set one of the
>pins HIGH, it must stay in that state, without a single glitch,
>until told to go low. This pin is actually supplying the bias
>voltage to the input transistor in an oscillator stage, so a
>momentary interruption of that voltage is going to play havoc with
>the oscillators.
>
>Is there a way to wire up a filter circuit, or maybe just a cap or
>two, that would effectively isolate a downstream component from the
>intermittent "toggles"?
>
>thanks, and I hope you know what I am talking about !!8-)
>
>Jim D. Martin


Hi Jim,

Exactly.

However, the pins do not go LOW. They become inputs. That is an
important distinction. The usual solution is one of the following:
1) provide a pullup resistor at the input to your oscillator circuit
sufficient to maintain it in operation during the glitch. The pullup
will hold the circuit at a high level.
2) put a capacitor in parallel sufficient to hold the voltage for the
~18 milliseconds duration of the glitch. The capacitor will hold
whatever level the BASIC Stamp gave it, provided your circuit does
not draw too much current.


This glitch is a characteristic of the microprocessor underlying the
Stamps. It occurs when the Stamp is reset, and during the execution
of the SLEEP, NAP or END instructions. All i/o pins becomes inputs
for a brief instant when the Stamp wakes up. During a long SLEEP
interval for example, the stamp wakes up once every ~2 seconds to
check on its status. For ~18 milliseconds each time, all pins become
inputs, and then they revert back to their programmed state as HIGH,
LOW or INPUT.

-- best regards
Thomas Tracy Allen PhD
electronically monitored ecosystems
http://www.emesystems.com
mailto:tracy@e...