Can some one please help with BS2x + allegro 6818
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Posts: 46,084
I am trying to communicate to allegro 6818
with BS2x, Has anyone done this or know the
protocal for doing so. I cannot find the info
on communicating with that chip. The address
for the pins are 32bits long. Do I send it MSB
or LSB and do I need to send all 32 or can I send
just 16 if thats all I need? The info is there
I am sure but I just dont see it!!!
If anyone has any ideas, please let me know!!!
Thanks so much
Gill
First Page;
http://www.allegromicro.com/sf/6818/
Full Data Sheet;
http://www.allegromicro.com/datafile/6818.pdf
Info from Page 1 of data sheet;
The A6818- devices combine a 32-bit CMOS shift register, accompanying data
latches and control circuitry with bipolar sourcing outputs and pnp active
pull downs. Designed primarily to drive vacuum- fluorescent displays, the 60
V and -40 mA output ratings also allow these devices to be used in many
other peripheral power driver applications. The A6818- features an increased
data input rate (compared with the older UCN/UCQ5818-F) and a controlled
output slew rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical
serial-data input rates are up to 33 MHz.
A CMOS serial data output permits cascade connections in applications
requiring additional drive lines. Similar devices are available as the
A6809- and A6810- (10 bits), A6811- (12 bits), and A6812- (20 bits).
The A6818- output source drivers are npn Darlingtons, capable of sourcing up
to 40 mA. The controlled output slew rate reduces electro- magnetic noise,
which is an important consideration in systems that include
telecommunications and/or microprocessors and to meet government emissions
regulations. For inter-digit blanking, all output drivers can be disabled
and all sink drivers turned on with a BLANKING input high. The pnp active
pull-downs will sink at least 2.5 mA.
Three temperature ranges are available for optimum performance in commercial
(suffix S-), industrial (suffix E-), or automotive (suffix K-) applications.
Package styles are provided for through-hole DIP (suffix -A) or minimum-area
surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power
dissipation, and low output-saturation voltages allow these devices to drive
most multiplexed vacuum-fluorescent displays over the maximum operating
temperature range.
Info from Page 5;
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Thanks Gill
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp
with BS2x, Has anyone done this or know the
protocal for doing so. I cannot find the info
on communicating with that chip. The address
for the pins are 32bits long. Do I send it MSB
or LSB and do I need to send all 32 or can I send
just 16 if thats all I need? The info is there
I am sure but I just dont see it!!!
If anyone has any ideas, please let me know!!!
Thanks so much
Gill
First Page;
http://www.allegromicro.com/sf/6818/
Full Data Sheet;
http://www.allegromicro.com/datafile/6818.pdf
Info from Page 1 of data sheet;
The A6818- devices combine a 32-bit CMOS shift register, accompanying data
latches and control circuitry with bipolar sourcing outputs and pnp active
pull downs. Designed primarily to drive vacuum- fluorescent displays, the 60
V and -40 mA output ratings also allow these devices to be used in many
other peripheral power driver applications. The A6818- features an increased
data input rate (compared with the older UCN/UCQ5818-F) and a controlled
output slew rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply, typical
serial-data input rates are up to 33 MHz.
A CMOS serial data output permits cascade connections in applications
requiring additional drive lines. Similar devices are available as the
A6809- and A6810- (10 bits), A6811- (12 bits), and A6812- (20 bits).
The A6818- output source drivers are npn Darlingtons, capable of sourcing up
to 40 mA. The controlled output slew rate reduces electro- magnetic noise,
which is an important consideration in systems that include
telecommunications and/or microprocessors and to meet government emissions
regulations. For inter-digit blanking, all output drivers can be disabled
and all sink drivers turned on with a BLANKING input high. The pnp active
pull-downs will sink at least 2.5 mA.
Three temperature ranges are available for optimum performance in commercial
(suffix S-), industrial (suffix E-), or automotive (suffix K-) applications.
Package styles are provided for through-hole DIP (suffix -A) or minimum-area
surface-mount PLCC (suffix -EP). Copper lead frames, low logic-power
dissipation, and low output-saturation voltages allow these devices to drive
most multiplexed vacuum-fluorescent displays over the maximum operating
temperature range.
Info from Page 5;
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Thanks Gill
_________________________________________________________________
Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp