Erratic pins
Help !?
I've been trying to add some extra sensor hardware to my StampBug (yes, I'm
a newbie !) but haven't achieved sensible results yet.
I couldn't figure out why my sensors were sending crazy signals to the stamp
and, through debugging, it looks like the I/O pins are toggling high/low ON
THEIR OWN. This continues to happen even when the sensors are not connected
!
In addition, I have run a very small diagnostic program to interrogate the
status of the I/O pins. All it does is debug the binary patterns from INS
and DIRS in an infinite loop. I expected to see these patterns remaining
static but they don't - is this normal ?
Either I've done something stupid or another problem is causing these
symptoms.
I'm running a BS2 on the Stamp2Bug expansion board.
Any advice would be most gratefully received.
Thanks in advance,
Justin.
I've been trying to add some extra sensor hardware to my StampBug (yes, I'm
a newbie !) but haven't achieved sensible results yet.
I couldn't figure out why my sensors were sending crazy signals to the stamp
and, through debugging, it looks like the I/O pins are toggling high/low ON
THEIR OWN. This continues to happen even when the sensors are not connected
!
In addition, I have run a very small diagnostic program to interrogate the
status of the I/O pins. All it does is debug the binary patterns from INS
and DIRS in an infinite loop. I expected to see these patterns remaining
static but they don't - is this normal ?
Either I've done something stupid or another problem is causing these
symptoms.
I'm running a BS2 on the Stamp2Bug expansion board.
Any advice would be most gratefully received.
Thanks in advance,
Justin.
Comments
left floating. When my students plug wires into CMOS input pins and leave
the wire sticking up like an antenna, the pins toggle as you pass your hand
by them. The pins are detecting their electric fields and are being fooled
into thinking they are plugged into Vcc or ground. If you plug the wires
into Vcc or Gnd, then the problem goes away. I wonder if this is happening
for you. One way to check is to run your test again, but this time, plug
wires into the breadboard for the BS2 I/O pins. Leave the other ends of the
wires sticking up. Now run your program but only monitor one pin to keep it
simple. I'd sample it every 1/10th second. Observe what happens when you
bring your hand near the wire. Also watch what happens when you stand well
away from the wire.
If the pin toggles when you move around it, but doesn't (or seldomly) when
you're no where near the wire, then the electric field of your body is
disturbing the BS2.
This is the risk of leaving pins floating. Use pull up or pull down
resistors to force an I/O pin either high or low until it is intentionally
connected to ground or power.
Paul
> I couldn't figure out why my sensors were sending crazy
> signals to the stamp
> and, through debugging, it looks like the I/O pins are
> toggling high/low ON
> THEIR OWN. This continues to happen even when the sensors are
> not connected
> !
>
> In addition, I have run a very small diagnostic program to
> interrogate the
> status of the I/O pins. All it does is debug the binary
> patterns from INS
> and DIRS in an infinite loop. I expected to see these
> patterns remaining
> static but they don't - is this normal ?
Regards,
Justin.
Original Message
From: Paul Verhage [noparse]/noparse]mailto:[url=http://forums.parallaxinc.com/group/basicstamps/post?postID=aQOzxYRTsF2vEoXLYv8XoZBX0S8OFF8Q22yjsgcsSQGSjxO6mZB5gzuYwtq_eogIyFPtI6IqxymKfSTzMqGEJACI]pverhage@s...[/url
Sent: 05 March 2001 17:55
To: 'basicstamps@yahoogroups.com'
Subject: RE: [noparse][[/noparse]basicstamps] Erratic pins
One thing I see in my electronics class is CMOS pins toggling when they are
left floating. When my students plug wires into CMOS input pins and leave
the wire sticking up like an antenna, the pins toggle as you pass your hand
by them. The pins are detecting their electric fields and are being fooled
into thinking they are plugged into Vcc or ground. If you plug the wires
into Vcc or Gnd, then the problem goes away. I wonder if this is happening
for you. One way to check is to run your test again, but this time, plug
wires into the breadboard for the BS2 I/O pins. Leave the other ends of the
wires sticking up. Now run your program but only monitor one pin to keep it
simple. I'd sample it every 1/10th second. Observe what happens when you
bring your hand near the wire. Also watch what happens when you stand well
away from the wire.
If the pin toggles when you move around it, but doesn't (or seldomly) when
you're no where near the wire, then the electric field of your body is
disturbing the BS2.
This is the risk of leaving pins floating. Use pull up or pull down
resistors to force an I/O pin either high or low until it is intentionally
connected to ground or power.
Paul
> I couldn't figure out why my sensors were sending crazy
> signals to the stamp
> and, through debugging, it looks like the I/O pins are
> toggling high/low ON
> THEIR OWN. This continues to happen even when the sensors are
> not connected
> !
>
> In addition, I have run a very small diagnostic program to
> interrogate the
> status of the I/O pins. All it does is debug the binary
> patterns from INS
> and DIRS in an infinite loop. I expected to see these
> patterns remaining
> static but they don't - is this normal ?
Your use of Yahoo! Groups is subject to http://docs.yahoo.com/info/terms/
You are right, of course. However, there is another good reason to not leave
pins floating.
In the old days of logic families like TTL, an inverter would be a single
transistor and a pull up resistor (well, not exactly a resistor, but close
enough for this discussion). When the input to the transistor was off (0),
the pull up resistor dominates the output and you get an on (1) at the
output. When the transistor turns on, it overpowers the pull up and you get
a 0 state. Think of the transistor as a switch (maybe part of a fake relay).
Switch off, output pulled up. Switch on, output at ground.
This accounts for two TTL behaviors. First, You never really get 5V and 0V
out of a TTL gate. The more current you pull the more drop through the
resistor (on a 1) and the lower the "5V" drops. A saturated transistor might
go to .2 or .3V so that is your zero level. (And you thought they just did
that to annoy you.) So while you can think of the transistor as a switch, it
isn't a very good switch.
The other thing this accounts for is power consumption. Even a disconnected
output pin draws power at the zero state. You are Since transistors are sort
of leaky, even a 1 output not connected to anything draws some power too.
Now comes CMOS. A CMOS output is two transistors. Think of them as switches.
The top switch connects to 5V and the output. The bottom switch connects to
the output and ground. ONLY ONE SWITCH IS ON A TIME. That's the
complimentary part. The transistors are built so that one turns on when it
sees a 0 and the other turns on when it sees a 1.
Now you get very nice 0 and 5V swings because the FETs are much better
switches than an old bipolar transistor. But here's the kicker: If you don't
have anything hooked up to the output, in theory, no power is drawn. There
is no complete ground return circuit, just a switch. This is why CMOS can
last for years on a battery -- very low power drain. However, when you
switch between 0 and 1 (or 1 and 0) there is a small amount of time when
both transistors might be on at the same time (or at least sort of on).
That's why the faster you drive CMOS, the more power it draws. You get
little tiny spikes of current draw just at the instant the transistors
switch.
Now, what's this long-winded explanation have to do with the original
question? Simple. When you leave a pin floating, you could get in the
condition where both transistors are on at the same time. The FET gates are
very hi-z so it is easy to imagine them getting 2.5V or so on them and
letting both transistors turn on and stay on. This can lead to excess
current consumption and -- at worse case -- exceeding the maximum current
rating and burning up a bond wire or otherwise damaging the chip. If the
gate voltage rises above Vdd (or below Vss) and there is no input clamping
(some chips have clamping diodes on the inputs to prevent this) you can
cause latch up. This is when the structures inside the chip accidentally
form an SCR that latches on hard and begin drawing power straight to the
grounded substrate. This is a sure prescription for a chip that will burn
up. We have actually cooked the lettering off of a 6805 like this and melted
several solderless breadboards.
OK, so that's my $.02 on that subject. Don't leave inputs floating. Lots of
good reasons why!
Al Williams
AWC
* Expand your Stamp I/O: http://www.al-williams.com/awce/pak3.htm
Anyway, the problem seemed to be caused (or exacerbated) by mis-matched
grounds ! I guess this is a way of life in newbieville.
Seriously though, thanks for your responses to my plea for help. Who knows,
perhaps one day I can repay the favour.
Regards,
Justin.
Original Message
From: Al Williams [noparse]/noparse]mailto:[url=http://forums.parallaxinc.com/group/basicstamps/post?postID=wKk-0oRm4QUhLpFeCRKj_MjvXE1TFGbwyhk2A0MvcU_BgxQu4n9i1lfea7jULdzZd-KwsZOs_lsCD-SbCKg]alw@a...[/url
Sent: 05 March 2001 20:05
To: basicstamps@yahoogroups.com
Subject: RE: [noparse][[/noparse]basicstamps] Erratic pins
Hi Paul,
You are right, of course. However, there is another good reason to not leave
pins floating.
In the old days of logic families like TTL, an inverter would be a single
transistor and a pull up resistor (well, not exactly a resistor, but close
enough for this discussion). When the input to the transistor was off (0),
the pull up resistor dominates the output and you get an on (1) at the
output. When the transistor turns on, it overpowers the pull up and you get
a 0 state. Think of the transistor as a switch (maybe part of a fake relay).
Switch off, output pulled up. Switch on, output at ground.
This accounts for two TTL behaviors. First, You never really get 5V and 0V
out of a TTL gate. The more current you pull the more drop through the
resistor (on a 1) and the lower the "5V" drops. A saturated transistor might
go to .2 or .3V so that is your zero level. (And you thought they just did
that to annoy you.) So while you can think of the transistor as a switch, it
isn't a very good switch.
The other thing this accounts for is power consumption. Even a disconnected
output pin draws power at the zero state. You are Since transistors are sort
of leaky, even a 1 output not connected to anything draws some power too.
Now comes CMOS. A CMOS output is two transistors. Think of them as switches.
The top switch connects to 5V and the output. The bottom switch connects to
the output and ground. ONLY ONE SWITCH IS ON A TIME. That's the
complimentary part. The transistors are built so that one turns on when it
sees a 0 and the other turns on when it sees a 1.
Now you get very nice 0 and 5V swings because the FETs are much better
switches than an old bipolar transistor. But here's the kicker: If you don't
have anything hooked up to the output, in theory, no power is drawn. There
is no complete ground return circuit, just a switch. This is why CMOS can
last for years on a battery -- very low power drain. However, when you
switch between 0 and 1 (or 1 and 0) there is a small amount of time when
both transistors might be on at the same time (or at least sort of on).
That's why the faster you drive CMOS, the more power it draws. You get
little tiny spikes of current draw just at the instant the transistors
switch.
Now, what's this long-winded explanation have to do with the original
question? Simple. When you leave a pin floating, you could get in the
condition where both transistors are on at the same time. The FET gates are
very hi-z so it is easy to imagine them getting 2.5V or so on them and
letting both transistors turn on and stay on. This can lead to excess
current consumption and -- at worse case -- exceeding the maximum current
rating and burning up a bond wire or otherwise damaging the chip. If the
gate voltage rises above Vdd (or below Vss) and there is no input clamping
(some chips have clamping diodes on the inputs to prevent this) you can
cause latch up. This is when the structures inside the chip accidentally
form an SCR that latches on hard and begin drawing power straight to the
grounded substrate. This is a sure prescription for a chip that will burn
up. We have actually cooked the lettering off of a 6805 like this and melted
several solderless breadboards.
OK, so that's my $.02 on that subject. Don't leave inputs floating. Lots of
good reasons why!
Al Williams
AWC
* Expand your Stamp I/O: http://www.al-williams.com/awce/pak3.htm
Your use of Yahoo! Groups is subject to http://docs.yahoo.com/info/terms/