The active edge for BS2 clock

Archiver

Hello,
Which is the active edge for BS2 clock , the rising edge or the falling
edge.

Thank You
Mohamed RefkY
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Archiver

It can shiftin both low or high for low you would use one extra
bit,byte
for low conversion
shiftin data,clk,msbpost,[noparse][[/noparse]datain/9]
for high conversion
shiftin data,clk,msbpost,[noparse][[/noparse]datain/8]

Mohamed REFKY wrote:
>
> Hello,
> Which is the active edge for BS2 Shiftout/shiftin clock , the rising edge or
> the falling edge.I will use A/D have an input that should be high or low
> according to the active edge for the processor clock.
>
> Thank You
> Mohamed RefkY
>
> ________________________________________________________________________
> Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com

Archiver

Hello,
Which is the active edge for BS2 Shiftout/shiftin clock , the rising edge or
the falling edge.I will use A/D have an input that should be high or low
according to the active edge for the processor clock.

Thank You
Mohamed RefkY

________________________________________________________________________
Get Your Private, Free E-mail from MSN Hotmail at http://www.hotmail.com

Archiver

> Hello,
> Which is the active edge for BS2 Shiftout/shiftin clock , the rising edge
or
> the falling edge.I will use A/D have an input that should be high or low
> according to the active edge for the processor clock.
>
> Thank You
> Mohamed RefkY


Well, both edges are active in the stamp implementation.

For SHIFTIN, the stamp generates each clock pulse (both a rising edge and a
falling edge), and then samples the input, and then another complete pulse
with a rising and a falling edge, then another sample, and so on for as
many bits as you specify.

For example,
SHIFTIN 0,1,msbpre,[noparse][[/noparse]x\6]
the timing looks like this:

time--->
chip select ~~~|________________________________________|~~~~

clock pre _______|~|___|~|___|~|___|~|___|~|______
^ ^ ^ ^ ^ ^
samples, msbpre 5 4 3 2 1 0

clock post _______|~|___|~|___|~|___|~|___|~|___|~|___
^ ^ ^ ^ ^ ^
samples, msbpost 5 4 3 2 1 0

In MSBPRE, the stamp takes the first sample after the chip select is
asserted, but before the first of five clock pulses. If you specify
MSBPOST, the stamp waits until after the first clock pulse to take the
first sample, and there is one additional clock pulse to get the sixth data
byte. The external device can shift out new data bits on either the rising
edge or the falling edge of the clock, it doesn't matter, the stamp will
understand.

The clock for SHIFTOUT is also both a rising and a falling edge,
coordinated with each outgoing data bit. Here is a picture for shifting
out 6 bits %100110:
SHIFTOUT 0,1,msbfirst,[noparse][[/noparse]x\6]


clock _______|~|___|~|___|~|___|~|___|~|___|~|___

data ____|~~~~~|___________|~~~~~~~~~~~|____________
bit 1 0 0 1 1 0
5 4 3 2 1 0

The data changes between, never during the clock pulses. The external
device can accept the data on either the rising edge or the falling edge of
the clock, it doesn't matter, because the data provided by the stamp is
stable for both clock edges.

Confusion arises because some devices like analog to digital converters or
the MAX3100 UART have the capability to shift in a command and shift out
the result of the previous command simultaneously, one on the rising edge
of the clock and the other on the falling edge of the same clock pulse.
The stamp cannot both receive and transmit at the same time, so, forget it.
With the stamp you first SHIFTOUT a command, and subsequently SHIFTIN the
result of the command.

I hope that helps,

- Tracy Allen
Electronically Monitored Ecosystems
http"//www.emesystems.com