Bs2 - cd74hc165 shiftin?
On 24 Mar 00 at 16:16, Ronald Doctors wrote:
> I am stuck tryingto use the CD74HC165 8bit parallel in serial out
> shift register. with the shiftin command and a BS2. I am using
> pin0 for the clock ( pin2 on the 165 )and stamp pin1 for datap (
> pin9 on the 165 ) I have PL L and CE L, regardless of what I apply
> to the input D0-D7 I get a zero out.
Bits will not be clocked out of the shift register while PL is
active (low), no matter what you do with the clock input. Bring PL
high to lock in the parallel data then present at D0 - D7, then leave
PL high while using SHIFTIN to bring the eight bits into the Stamp.
That will presumably mean another Stamp pin to control PL, unless you
have some other signal source for this purpose.
> If I connect the datap to 5.0 volts I get all 1's.
Not a good idea. Pin 9, which you referred to as datap in first
paragraph, is an _output_ from the chip. You don't want to connect
+5 directly to an output...
> I am puzzled by the DS pin but I have it tied L.
Whenever bits are clocked out serially, the logic level present at
this (input) pin is shifted in to the vacated bit positions. This
allows the '165 to also load data serially via this pin. Sounds like
a feature you don't need for your application.
A suggestion if you have the pins to spare. Connect eight Stamp pins
to D0 - D7 in addition to the connections to the clock, data and PL
pins. Use the Stamp to generate patterns on the D0 - D7 inputs which
you can then turn around and clock back into the Stamp. When your
input consistently matches what you know the chip is being presented
with, you have mastered the input process. Then configure your real
input source to the '165.
Steve
> I am stuck tryingto use the CD74HC165 8bit parallel in serial out
> shift register. with the shiftin command and a BS2. I am using
> pin0 for the clock ( pin2 on the 165 )and stamp pin1 for datap (
> pin9 on the 165 ) I have PL L and CE L, regardless of what I apply
> to the input D0-D7 I get a zero out.
Bits will not be clocked out of the shift register while PL is
active (low), no matter what you do with the clock input. Bring PL
high to lock in the parallel data then present at D0 - D7, then leave
PL high while using SHIFTIN to bring the eight bits into the Stamp.
That will presumably mean another Stamp pin to control PL, unless you
have some other signal source for this purpose.
> If I connect the datap to 5.0 volts I get all 1's.
Not a good idea. Pin 9, which you referred to as datap in first
paragraph, is an _output_ from the chip. You don't want to connect
+5 directly to an output...
> I am puzzled by the DS pin but I have it tied L.
Whenever bits are clocked out serially, the logic level present at
this (input) pin is shifted in to the vacated bit positions. This
allows the '165 to also load data serially via this pin. Sounds like
a feature you don't need for your application.
A suggestion if you have the pins to spare. Connect eight Stamp pins
to D0 - D7 in addition to the connections to the clock, data and PL
pins. Use the Stamp to generate patterns on the D0 - D7 inputs which
you can then turn around and clock back into the Stamp. When your
input consistently matches what you know the chip is being presented
with, you have mastered the input process. Then configure your real
input source to the '165.
Steve