Spi-ish question

R Baggett

So, I just tried to use jm_ez_spi to operate a TPIC6595 (Shift register with open drain high voltage/current outputs.

I tried slowing things way down (1 khz) and still had some strange going on.

So here is what happens:
In the attached archive I have 'Hardware_00' with 3 possible tests that can be selected in 'Setup()'

Test1 After fiddling around, and then turning ALL outputs on and off, this works. see Test.png where yellow is clock, cyan is data. magenta, is output latch load, green is output. it works

Test3 is with the outputs alternated. it does not work. It is my understanding that spi clocks data in on the falling edge of the clock, and the waveform looks perfect for this interpretation. It just doesn't work..

From this I surmised that the chip wants to clock on the leading edge of the clock, so I built Test 2, which works just fine, but ignores the special capabilities of the P2.

so, my question is:
Can the SPI mode be adjusted to land the clock in the middle of the data? or switch edges?

Rayman

Hmm... There is a polarity inversion flag in the smartpins. Maybe that would fix it?