Uses for clocked/feedback pin modes?

n_ermosh

Every time I read the P2 docs I discover yet another thing it can do. What an amazing piece of hardware. I’ve been trying to collect and keep note of all the creative ways the hardware can be used, as it can drive good inspiration for creative design.

One of the things that I have yet to really understand a good use for is the clocked and feedback modes in the smart pins. What are some clever things people have done with those to maybe reduce external hardware, reduce software, or otherwise just get an interesting result?

Wuerfel_21

"clocked" modes are ones with the P_SYNC_IO bit set. I think the original idea is to compensate for the variable propagation delay in the core with an additional register stage. In practice it has the interesting effect that the clocked pins are sampled half a cycle later than normal. This becomes important when dealing with high-speed interfaces like the PSRAM. If each bit is only on the bus for 2 cycles, then it becomes very likely that both possible sampling postions in normal (P_ASYNC_IO) mode are c‌rap (i.e. missing the center of the eye pattern). Enabling clocked mode offers 2 more sampling positions. That makes 4 overall possible positions (2 async+2 sync), one of which must be close to the ideal center.

evanh

Probably the chief function is for an externally constructed sigma-delta ADC, like how the Prop1 did it. The feedback component is good for various oscillators in general.