P28-P31 P2 pin usage question

rogloh

Had a question on the usage of the upper nibble on P2-EVALs and maybe early P2-Edges:

Given the problem as it exists is it an output only issue or would using these pins as high speed inputs for signals with frequent transitions also cause noise for the crystal supply and cause PLL jitter? I'm considering making up a board that may have some ~27MHz transitions and I'd kind of like to route one clock signal in particular to P31 in order to gain fast access of the top bit of the INA port data using the C flag with a "mov reg, ina wc" instruction.

I guess I can try to prototype it first somehow, but I'm hopeful that if the pin is not an output actively being driven by the P2, but rather used as an input, then the shared VIO supply pin for this top nibble may not be as noisy and affect the crystal signals, though I'm not exactly sure because some ground return current for this pin will also be affected by an input feeding it.