Power decoupling and P2 Edge
ke4pjw
Posts: 1,115
in Propeller 2
I am modeling my next board after the P2 Edge and the decoupling caps have me a bit confused on the VIO supplies. Like the caps used on the VDD, they are 4.7uf. That seems to be a bit large for decoupling, isn't it?
Also, is the primary reason for using many small LDOs with limited output for VIO supply to ensure that you won't "over current" the VIO if a pin is shorted on output?
As always, thanks in advance!
--Terry
Comments
I think the idea is modern MLCC parts are good for high frequency too. Basically, no longer need to use the smaller values unless their smaller footprint is desired in tight places to get the needed proximity that is also required for high frequency decoupling.
Also, include footprint size as a metric - the smaller the footprint, the lower the impedance.
Broadly speaking for decoupling with SMT MLCC's, for any footprint size cap < 0603, the best value of capacitance would be the largest capacitance value in that footprint that is affordable.
Thinking only in terms of capacitance is a bit "old school", based on the good old days of large & leggy parts; sure with big TH ceramics then a monstrous cacophony of tiny values was essential to overcome lead length.
Why 4.7uF? At the time of that design, they hit the sweet-spot of cost vs capacitance (taking into account voltage rating/bias). 10uF's were significantly more expensive considering the qty (might still be). 1uF at >=10V would be fine for many designs too. By using the 4.7uF (in 0402 package) we got decoupling and also some distributed bulk capacitance, which saved on having numerous larger caps around the board.
The LDO's have a few benefits, including...
Consistent current availability, protection and noise isolation per IO group
Failsafe design - damage to one IO group need not bring down the entire system
Spread of heat around the board, instead of a honking heat source in one place that's harder to dissipate and detrimental to the P2's top operating speed
BOM cost saving vs using single large switcher and multiple beads/etc.. to isolate each VIO group
Using smaller footprints also helps to place them closer to the P2. But keep in mind that it's not the distance that makes HF performance worse but the area inside the traces of the power connection and ground return path. This is why a multilayer PCB is much better. A capacitor with the power connection routed on the top layer and the ground plane directly underneath spans a very small area and therefor has very little inductance in the loop.
Watch this video!
Indeed - and relatedly where Via's are used, placement is critical. Stitched inside the cap pads is usually most ideal. Although not always practical with tiny parts, where the vias might be alongside the cap pads, but still as close to the center as possible.
Using 1 uF on my SimpleP2 board, 0805, and it seems to be fine. I have a place for closer ones on bottom of board, but I saw absolutely no difference in performance when those were populated with 100 nF, 1 uF, or 10 uF.
One thing that I think it was @evanh said, is that you want to pay special attention to the pin group where the crystal is. I added an extra 100 nF there...
I generally recommended limiting the types of uses for that group, rather than trying to buff it. ie: Use those pins for inputs or DAC outputs or just lower drive strength are all good options. Basically, anything except full strength digital outs.
And what Vons did with the revised breakout boards was good too. Removing the 5 Volt pin from that group removes one more easy way to destroy a critical VIO rail.
That is a good point @evanh , I killed a pin group with eval type header by accidentally touching 5v to an io pin. Bad news…
A little too easy to do
@Rayman if you are using an oscillator module instead of a crystal, do you still have issues with using those pingroups for highspeed IO? Does it affect only P32-P35 or P28-P35?
Seems like proper decoupling on VDD9 would keep problems from occurring on pins 32-35 and XI, because it separates XI from P32. Any return currents induced into VDD_9 would pass to the ground layer through the decoupling cap and not make their way to XI. It doesn't look like you can do anything for P31 because it is directly adjacent to XO.
At this point I think I am handwringing on stuff that isn't going to be a problem. I need to just lay it out completely, do a "Full Send", see what doesn't work, and iterate.
My board never had the issue with high speed IO near crystal.
I did try an oscillator to see if it would increase overclocking freq, but it didn't...
Just using a crystal would reduce complexity and part count. Any downsides to using crystal vs a TCXO?
It is all about P28..P31. But distance along the common supply mattered. So on the tested Eval Boards there was a measurable difference between P24..P27 and P28..P31. Sysclock frequency instability was still measurable even using those farther four pins. I think there was even a difference between using P30 vs P31 with P31 as the most sensitive.
P32 had no problem. Different supply and different pin group. But if using a commoned supply for all surrounding pin groups then one would expect interference from P32 too.
Sounds good for beyond P28..P31.
PS: With the PLL operating, it manifested as a clock jitter issue. It wasn't all that obvious unless you were looking for jitter.
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