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Christmas puzzle: SQI bit shuffler — Parallax Forums

Christmas puzzle: SQI bit shuffler

ManAtWorkManAtWork Posts: 2,098
edited 2023-12-23 16:01 in Propeller 2

For those of you who tend to get bored during the christmas holidays when the weather is rainy and all shops, bars, gyms etc. are closed I have a riddle to solve.

As input we have two longwords. The first contains an 8 bit command and a 16 bit address. The second contains 32 bits of data. They have to be transmitted over an SQI interface with four data lines SD0..3. The rules are:

  • all bytes are transmitted with the most significant bit (MSb) first
  • the address is in big-endian format (MSByte transmitted first)
  • data is in little-edian format (LSB first)
  • the P2 smart pins (P_SYNC_TX mode) transmit the LSb first

So if we write the input as 32 bit binary numbers with one character representing a binary digit we have:

don't care command  address         ; data
  ~~~~~~~~ XWVUTSRQ PONMLKJIHGFEDCBA; vutsrqpo nmlkjihg fedcba98 76543210

and we need the following output:

d0 = ~~~~~~~~~~~~~~~~ ~~ osgk8c04 AEIMQU
d1 = ~~~~~~~~~~~~~~~~ ~~ pthl9d15 BFJNRV
d2 = ~~~~~~~~~~~~~~~~ ~~ quimae26 CGKOSW
d3 = ~~~~~~~~~~~~~~~~ ~~ rvjnbf37 DHLPTX

The challange is to find a sequence of P2 assembler instructions that calculates the valid output (4 registers d0..d3) from the input (registers cmdadr, data). The one who comes up with the shortest and most elegant solution wins a KISS board.

(Hint: I think I have a solution with 16 instructions)

Comments

  • I don't really need any more, but oh well

    ' cmdadr is ~~~~~~~~_XWVUTSRQ_PONMLKJI_HGFEDCBA
    ' data is vutsrqpo_nmlkjihg_fedcba98_76543210
    
    rev data ' 01234567_89abcdef_ghijklmn_opqrstuv
    movbyts data,#%%0123 ' opqrstuv_ghijklmn_89abcdef_01234567
    splitb data ' osgk8c04_pthl9d15_quimae26_rvjnbf37
    getbyte d0,data,#3 ' ~~~~~~~~_~~~~~~~~_~~~~~~~~_osgk8c04
    getbyte d1,data,#2 ' ~~~~~~~~_~~~~~~~~_~~~~~~~~_pthl9d15
    getbyte d2,data,#1 ' ~~~~~~~~_~~~~~~~~_~~~~~~~~_quimae26
    getbyte d3,data,#0 ' ~~~~~~~~_~~~~~~~~_~~~~~~~~_rvjnbf37
    
    rev cmdadr ' ABCDEFGH_IJKLMNOP_QRSTUVWX_~~~~~~~~
    splitb cmdadr ' AEIMQU~~_BFJNRV~~_CGKOSW~~_DHLPTX~~
    rolbyte d0,cmdadr,#3 ' ~~~~~~~~_~~~~~~~~_osgk8c04_AEIMQU~~
    rolbyte d1,cmdadr,#2 ' ~~~~~~~~_~~~~~~~~_pthl9d15_BFJNRV~~
    rolbyte d2,cmdadr,#1 ' ~~~~~~~~_~~~~~~~~_quimae26_CGKOSW~~
    rolbyte d3,cmdadr,#0 ' ~~~~~~~~_~~~~~~~~_rvjnbf37_DHLPTX~~
    
    shr d0,#2
    shr d1,#2
    shr d2,#2
    shr d3,#2
    
    

    17 instructions, 34 cycles

  • ManAtWorkManAtWork Posts: 2,098
    edited 2023-12-23 16:56

    I think I have a 14 instruction solution.

    'input = 24 bits command + address, 32 bit data, MSB left justified
    'don't care command  address         ; data
    '  ~~~~~~~~ XWVUTSRQ PONMLKJIHGFEDCBA; vutsrqpo nmlkjihg fedcba98 76543210
    
    'step1: re-order bytes, big/little endian 
    ' XWVUTSRQ PONMLKJIHGFEDCBA 76543210; fedcba98 nmlkjihg vutsrqpo 76543210
      rolbyte  cmdadr,dat,#0
      movebyts data,#%01_10_11_00
    
    'step2: bitwise reverse both
    '01234567 ABCDEFGH IJKLMNOP QRSTUVWX; ~~~~~~~~ opqrstuv ghijklmn 89abcdef
      rev      cmdadr
      rev      data
    
    'step3: split bytes
    '04AEIMQU 15BFJNRV 26CGKOSW 37DHLPTX; ~~osgk8c ~~pthl9d ~~quimae ~~rvjnbf;
      splitb   cmdadr
      splitb   data
    
    'step4: extract bytes
      getbyte  d0,data,#3
      rolbyte  d0,cmdadr,#3
      getbyte  d1,data,#2
      rolbyte  d1,cmdadr,#2
      getbyte  d2,data,#1
      rolbyte  d2,cmdadr,#1
      getbyte  d3,data,#0
      rolbyte  d3,cmdadr,#0
    
    'output = 4 words of 14 bits each, first bit right justified
    'd0 = ~~ osgk8c04 AEIM QU
    'd1 = ~~ pthl9d15 BFJN RV
    'd2 = ~~ quimae26 CGKO SW
    'd3 = ~~ rvjnbf37 DHLP TX
    

    I need to verify that later....
    (Edit: fixed register names)

  • yea, that seems slightly smarter

  • One additinal instruction (getbyte d3,data,#0) could be saved if data and d3 are the same register.

    What annoys me a bit is that the SCLK pin has to be placed in the middle of the D1 and D2 pin so that all four can use the P_MINUS3_B to P_PLUS3_B input routing. That disables the use of ADDPINS to setup the four data pins at once and requires a lot more instructions.

  • This sort of thing is where you'd really want to use the streamer unit instead.

  • And the winner is... Ada (Wuerfel_21)
    ...sadly due to being the only participant.

    @Wuerfel_21 said:
    This sort of thing is where you'd really want to use the streamer unit instead.

    Yes, probably. I thought using the streamer was too complicated and the bit shuffling has to be done anyway. But setting up the smart pins also takes a lot of instructions. I'll have to try both versions to see which one performs better.

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