CFET - IC fabrication tech news
Reading the tech news and seen the announcements about "CFET" structure for future fabrication shrinks. For those that haven't read about it already - it's simply stacking CMOS's push-pull transistor pair one atop the other, NFET on top, PFET on bottom. Not sure if the order has explicit reason or not. This has the obvious advantage of trading height for surface area. So the transistors aren't individually any smaller but more can be packed in the same area anyway.
What surprised me the most is that this wasn't already a done thing decades ago.