Asking the requisite "is there software to make the P2 into a Logic Analyzer" question again
pedward
Posts: 1,642
in Propeller 2
Hi, Internet searches turn up P1 related stuff and a software based analyzer for testing your code, but I haven't seen anything for using the P2 as a LA.
Given the P2 has a lot of usable pins that would directly interface to 3.3-5v logic (with a gaggle of resistor blocks), it seems like an ideal platform for an analyzer.
I was dreaming of an S100 extender card with a right-angle P2 Edge connector that I could slot a module in, then sniff the S100 bus while I'm conducting testing and experiments.
Before you ask, it's a CNC control from the 80's, they roughly designed it around the S100 bus. It implements the bare minimum S100 functionality and has around 40 signals.
Comments
Yep, could be quite effective - even as a mixed signal scope. One streamer for 32 pins into hubRAM, two streamers would provide bulk store of same into partnering PSRAMs.
There is easy ways to trigger on pulse combinations during capture using smartpins. Pattern trigger is only possible via a cog bit-bashing, sadly, so a reduce max sample rate for this. In theory, can interleave cogs to raise the sample rate some.
Can employ variable drive strengths to interact with the I/O. Could even support 4 channel per streamer ADC sampling or just slower sampling on all pins - useful for quick verify that levels are fully rail to rail without needing to get a scope out. And of course any and all pins can be DAC driven as well. All reconfigurable on the fly.
Would be a lot of work to fully develop and there is already a lot of cheap USB based LAs around now.
Have you priced 32 channel analyzers? It makes my $20 HP 1651A even more of a bargain.
Salae charges ~$1500 for a 32 channel USB.
Hantek charges ~$230
There are lots of "cheap" 8 and 16 channel units.
Knowing what the P2 is capable of, I imagine it could do better, especially if you added a high speed USB chip to stream data.
I haven't looked at what options there might be in the world of USB controllers but a parallel interface mastered by the Prop2 would be best for the Prop2 itself. You're probably looking at a FPGA to glue everything ... which would make it just like any other then.
Ethernet might be wiser choice. ManAtWork did a 100 Mb/s RMII driver - https://forums.parallax.com/discussion/174351/rmii-ethernet-interface-driver-software/p1
Provides a nice isolated high frequency connection. Can sit it on the AC mains and still have reliable comms without needing to program other components.
OzPropDev made something pretty neat, thread is here.
https://forums.parallax.com/discussion/163967/propeller-2-logic-analyzer
Also, I have no idea how search doesn't throw up that (very useful) result when you try searching for "analyzer", "logic analyzer" etc. Something seems very broken
I referenced that in my first post, it's not a standalone analyzer, it's intended to debug programs by looking at their pin usage, from what I can tell. I want to sniff 48 input pins, not debug programs.
It should be relatively straightforward to do this using one of Sigrok's generic LA/scope interface protocols. Start with something slow over plain serial (but not on P62/63!), and then move to Ethernet later.
I still haven't gotten around to implementing TCP (or DHCP, or DNS, or anything else that requires timers to deal with retries) in the IP stack I started developing for @ManAtWork 's Ethernet PHY board...
It does sniff pins. Its from 7 years ago, before we had silicon, so the initial screenshot is towards the 'simulation' end. The later screenshot below (from that thread) is of real pins transitioning into ADC mode, because it makes for a simple demo with something 'real world', but you could turn off the smarts in the smartpin to see the basic digital inputs if thats what you need
Ozpropdev also did some debuggers, they were separate
You'll need two COGs for capturing that many signals and a way to resync them later. Each COG could stream into HUB (32 and 16 bits) and another couple of COGs would write back into PSRAM. Up to 32MB worth could be captured this way on the Edge but you'd have to factor some dead time due to memory bus overheads and the extra 16 bits. Hopefully you could get towards 100 Msample/s with ~330MHz P2 for example. One writer would have to write 2x the amount of data from HUB vs the other and you'd need to reassemble these blocks later.
Update. Doh! Just realized you can't capture 48 bits with PSRAM on the Edge. Not enough IO pins! You could do this with HUB RAM storage only, or some system with a smaller PSRAM bus width (at reduced bandwith). You could do 40 pins though on the Edge (if you want to read back serially to a PC... slow!).
The HP1651B that I have is 100Mhz 32 channels timing mode, and 35Mhz 32 channels in state mode. It only has 1024 samples per channel depth.
It seems trivial to reserve 32KB of memory for 32 channels in hub ram.
Obviously "modern" stuff needs more, but even with 4KB per channel you aren't breaking the bank.
TBH, I haven't touched any P2 stuff since 2012 or 2013, when P2_Hot ran on a DE0 Nano with a couple cores.
I've forgotten most of the capabilities of the P2 for advanced pin and features. I'm certain I could develop the software to do what I imagine, time is the factor.
For now, I've got an HP 1651B and an HP1631D, those should suffice, however I'm missing all the probes for the pods on the 1631
I've been experimenting with this on side for a bit. I implemented a basic (read: crude) logic analyzer implementing the SUMP protocol (OLS) which is serial port based which Sigrok/PulseView should support. I posted on another (the other?) thread I was going to post once stable... unfortunately software isn't playing nice and life things are getting in the way, but even on the side it's been nice to have as a readily available LA, even if it is a glorified tech demo implementation-wise, quite crude. There is some loose intent to pair this with some hardware in the near-ish future (sure...) hopefully and with all the PSRAM discussions I may need to look into all the commotion there... seems interesting.
Real reason I have been putting it off is I haven't been having luck with Sigrok/PulseView and it is a real bummer. SUMP is based on a serial port and Sigrok's serial library implementation appears unstable if not outright unusable. I can only rarely get it to work on Windows... and when it does it works once then you have to re-open the software else it returns stale data if at all. I tried Ubuntu with the hope that it'd work much better but that seems broken as well but differently, causing serial ports to disappear until re-plugged and whatnot. I eventually built a copy of the java OpenBench LogicSniffer client and it has been rock stable, even if outdated.
Note: I have had luck on those generic fx2 based LA's though with PulseView, even if bare-bone functionality.
Source: piInlineSerial.spin2
Demo: Demos/Demo_piLogicAnalyzer.spin2
Alt Client (Java, Unaffiliated): https://github.com/jawi/ols
I did find this ?
https://github.com/gillham/logic_analyzer/issues/38
and this ?
https://github.com/pico-coder/sigrok-pico
says
Use a raspberry pi pico (rp2040) as a logic analyzer and oscilloscope with sigrok. This implementation uses the pico SDK CDC serial library to communicate with sigrok-cli/pulseview through a sigrok driver.
so that shows people are using CDC serial interfaces for PC connections, but some patches are needed ?
This new module and MCU may change the 32 channel landscape ?
the WCH CH569 MCU uses USB3 SS built-in PHY (5Gbps) so manages High Speed Parallel Interface (HSPI) up to 3.8Gbps with unique fast bidirectional parallel bus 8, 16 & 32bits up to 120MHz
https://blog.adafruit.com/2022/12/08/testing-the-new-ch569-usb3-device-host-chip-usb-development/
Maybe the CH569 can be used for 8b or 16b PC link, depending on your overall pin budget.
That may be simpler than a local offload to PSRAM ?
I was looking at this one:
https://github.com/pschatzmann/logic-analyzer
C++ though... May or may not work with FlexProp C...
@pedward I picked up a 1660CS from a charity auction a month or so ago. It was more about helping the selling organisation than any immediate need. It came with excess leads (pods?) because whoever it belonged to was making some custom terminations, so perhaps I can spare those, given you're probably going to want your own custom terminations?
The 1660CS looks to use the same pods as the 1651. The 1631 uses permanently connected pods that have a .156 pitch IIRC. Ironically I found an auction for a manual and probes in the same city where I bought the LA years ago...but they want a bit too much for those parts.