Next attempt at a board that can hit 340 MHz --> Vdd all along...
Rayman
Posts: 14,737
So far, my P2 boards are just fine at 250 MHz. But, they all die above 320 MHz.
Frustratingly close to being able to run the @Wuerfel_21 emulators, but not quite there...
I'm not 100% sure it's thermal either, but maybe it is.
Anyway, gearing up for third version of this board and hoping that going from 2 to 4 layers will get me there. I'm pretty much keeping top and bottom the same and using one inner layer for 3.3V and one for 1.8 V. Also having a dedicated cap for every 3.3V and 1.8V pin, which may also help.
I do have some 5V signals on the 3.3V layer that I think I'll move to the 1.8V layer after looking at this.
Update: Seems to be able to run NeoYume and MegaYume game emulators, so maybe mission accomplished. Posting Eagle source and Gerbers here now.
Update2: Final version with LDO regulators on some pin groups posted here 11Nov23
Update3: New board running stable at 375 MHz after the @Tubular Vdd boost to 2.0 V. Old board benefit as well...
Comments
I think the parallax boards also use extra thick layers...
Also, assuming you'd want to run a RAM board on that double header, I'd overthink the routing. The trace lengths seem all over the place. Or I guess just put the RAM on the board, though that then eats that connector.
I'm sure 4 layers will help, Ray
It might pay to bring the caps closer near P28..31 as this is where the oscillator and its associated power draw is. Perhaps even have a couple of caps on VIO2831, eg 1uF and 10nF
@Tubular is oscillator draw 3.3 or 1.8 V?
Guess you are saying 3.3 V
Yes 3v3 as I understand it. I think Chip said that in one of the live forums some time ago.
@Wuerfel_21 i do want to take a look at squeezing in optional psram on the board …
You can also get thicker copper from most fabs for not much more, and much thicker copper for much more
#1
You could look to move the decoupling caps to the bottom side, so the loop lengths can greatly reduce.
You could try different stackups?
I'd guess the best heat spread will be with GND as the layer closest to the P2, with thinnest laminate giving shortest via paths. That gets the heat spread out, as quickly as possible.
Most designs have vias between the PAD rings and GND PAD, to keep core Vcc tight.
A small nudge up on Core Vcc can also increase MHz
#1 addit:
I checked, and it seems JLCPCB charge incrementally for above 1oz outer and 0.5oz inner and pcbway allow 1oz outer and 1.5oz inner but jump for any thicker than that.
JLCPCB do have this option (Adds $89 tho )
Copper paste filled an capped : Vias should be at most 0.5 mm in diameter to avoid incomplete filling, and at least 1.0 mm from unfilled PTHs/NPTHs to protect them from epoxy. Vias violating this clearance will be left unfilled.
Vias are filled with high thermal conductivity copper paste and then plated over to create a flat, solderable surface. The filling has an excellent heat conductivity of 8 W/m·K ideal for via-in-pad and heatsink pads.
If I tick all the thermally aggressive boxes, for fun, I get this from JLCPCB.
JLCPCB Special Offer $7.00 Via Covering $89.00 Surface Finish (ENIG) $17.30 Outer Copper Weight 2Oz $33.70 Inner Copper Weight 2Oz $34.00
Build Time PCB：3-4 days $0.00 Calculated Price $181.00
You could copper paste fill the GNDPAD vias and even via-in pad all the VCC and VIO pads into inner planes, for super low L and low thermal paths
ALLPCB are $71, for 2Oz all layers, vias tented but not copper paste filled, HASL, so broadly similar price points. (all for 5 panels at the nominal 100 x100)
I'm not sure adding more layers of FILL is going to help. By doing so you increasing the total parasitic capacitance which will help to act like a low pass filter. That low pass filter will snub the upper frequency you might otherwise be capable of. ... and as I have said before, your pushing the limits of 180nm technology when you get near 350MHz.
Are you talking about copper paste filled vias ?
I'm not seeing a low pass filter in the GND-PAD to ground plane thermal pathway that those vias provide ?
They fill with solder now, and via-in-pad helps lower the inductance and thermal pathways to the GND planes too.
We all understand that a cooler die can run faster ?
Was just looking at the crystal and not sure case should be grounded... Definitely shouldn't have both sides grounded, that makes a loop...
Use an integrated oscillator module rather than a plain crystal. It eliminates the XI pin noise injection problem and they are more common as tiny SMD parts that way anyway. And the prices are the same so there's really no advantage in using a plain crystal.
Beau kind of countered his own statement. He's talking about having large amounts of closely layered VDD and VSS across the whole board acting as a small but perfect capacitor.
Yes, I believe Parallax used heavier outer layers for greater heat-sinking. Not for electrical performance.
Rayman,
I did a mock-up a while back for a 4-layer 48/96 MB PSRAM accessory. It used a split 3v3 rail between VDDQ and VDD of the RAMs. It allowed the two LDO regulators from the two accessory headers to stay independent.
The point is, I went to some trouble to work out how to keep wide paths for both halves without needing an extra plane (which turned out easy to do in Kicad):
Further reading - https://forums.parallax.com/discussion/comment/1539947/#Comment_1539947
and https://forums.parallax.com/discussion/comment/1539907/#Comment_1539907
Was this XI pin noise injection problem a concern for maximum frequency or precision?
I see this on Digikey: https://www.digikey.com/en/products/detail/taitien/TXEAADSANF-20-000000/6127602
But, I also see Parallax added a buffer between oscillator and P2. Is that necessary?
That was because we used a 1.8V oscillator (to keep idle current* as low as possible), and it needs to drive the 3.3V XI level.
If you go with a 3.3V level osc, then buffer not required.
Edit: * By that I mean.... The osc runs all the time on the Edge, even if the P2 is held in reset or in low current modes/etc. The 3.3V parts available at the time of the last Edge rev had significant current requirements when compared to the 1.8V versions, and we wanted to have the "standby" current as low as possible, and as close to the original Edge specs which used the bog standard crystal.
Neither. Switching edges of full strength (FAST) outputs on pins P28..P31 inject a disturbance on VIO internally we think. This in-turn upsets the delicate threshold of XI when presented with a sine wave because XI is missing a Schmitt trigger circuit.
This - https://www.digikey.com/en/products/detail/jauch-quartz/O-20-0-JO32-B-1V3-1-T1-LF/10416199
It has CMOS output.
@evanh Will the part I found not work? I think it has a better stability spec...
I see the output voltage is only 0.8 V p-p. Maybe that's the problem?
Looks like I can add 0603 caps to the bottom layer pretty easily with a short path to the pins.
But, this does take away from thermal conduction from the ground pad...
Also, the giant keepouts of the 0603 parts appears to suggest I could just as easily use 0805 there too..
@evanh - "Beau kind of countered his own statement...." - No not really
"... He's talking about having large amounts of closely layered VDD and VSS across the whole board acting as a small but perfect capacitor." - No, that is actually beneficial... the large pours that are surrounding the P2 forming a huge ring are more what I am talking about. There are two things I see here 1) inductively this forms the equivalent of a shorted secondary coil on a transformer 2) the close proximity of ALL the metal to the chip can introduce capacitive parasitic effects within the chip. That "hole" where the P2 sits is definitely a hot spot for "fringe" capacitor effects. Any parasitic effects are not exclusively to ground, VSS and VDD should be viewed equally in terms of parasitic effects.
Reference: "What is Parasitic Capacitance in a Circuit Board" - good tips and insights
https://www.ourpcb.com/parasitic-capacitances.html
The hard stop for any of this is the technology process of 180nm. Due to parasitic capacitance and resistance on the substrate itself, the frequency is limited to about 350MHz
Reference: "MOSIS WAFER ACCEPTANCE TESTS" - RUN: T68B (MM_NON-EPI) - 363.77 MHz @ 1.8V
https://www.ee.iitm.ac.in/~nagendra/cadinfo/tsmc018_info.txt
Reference: "MOSIS PARAMETRIC TEST RESULTS" - RUN: T18H (LO_EPI) - 384.10 MHz @ 1.8V
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s02/Assignments/t18h_lo_epi-params-mod.txt
Added 0805 caps to ever power pin on the bottom layer. Not clear if this helps or hurts thermally. Might help with vias to power planes to get them involved with removing heat. But might hurt as taking away from ground plane near the P2 chip...
Also added place for oscillator, just outside of crystal, so can go either way...
That one is 20 MHz VCTCXO Clipped Sine Wave Oscillator, so it can be AC coupled direct to P2 XI, but it is then prone to the cross-talk PLL issues from active adjacent pins.
It is also a VCTCXO, which means you need to bias the control voltage pin1. A P2 DAC there allows you to fine trim and lock the VCTCXO
The P2 Edge amplifies the clipped sine and then drives P2, with a tiny logic gate.
The highest precision and lowest power oscillators tend to be clipped sine.
There is also parts like ECS-TXO-2520-33-200-AN-TR, which are CMOS and TCXO ±2.5ppm -40°C ~ 85°C, but of course cost a bit more than the jauch-quartz 50ppm part in #16
There is also a smaller 2520 O 20,0-JO22-B-1V3-1-T1-LF ( phase jitter 12 kHz ~ 20.0 MHz < 1.0 ps RMS)
LCSC has some SG-8018CG 20.000000MHz Seiko Epson 20MHz ±50ppm 1.8V~3.3V SMD2520-4P for a bit less $, but those have higher jitter.
They also show These - they are YSO110TR series, data does not define jitter, but google finds oblique : Period Jitter (@12K-20MHz). 1.8V=1.5ps 2.5V=1.1ps 3.3V=1ps ?
OT252020MJBA4SL Yangxing Tech 1.8V~3.3V ±10ppm 20MHz SMD2520-4P Oscillators ROHS 10+ US$0.463
OT201620MJBA4SL Yangxing Tech 1.8V~3.3V ±10ppm 20MHz SMD2016-4P Oscillators ROHS 10+ US$0.5107
Hmm, maybe their 'Oscillators' and 'Pre-programmed Oscillators' headings actually are valid now at lcsc, as the pre programmed one often have PLL that give higher jitter.
Thanks @jmg Think I'll try the part you recommended first. Don't think really need ppms in my applications... Although, maybe a problem if using as RTC clock...
Think I can squeeze in 64 MB of PSRAM on bottom of the board, bottom layer though.
Guess I'd use P32 as basepin and have two banks of 16-bits...
If you allow a dual-footprint OSC for eg 2520 and 2016 (or even 3225 too, since your board is not tiny) that covers more choices and you can fit differing OSC to different boards to compare.
Often generic (50ppm) oscillators are far better than the worst case margins.
Okay, gotcha. And I guess that's a reasonable source of the injected XI noise when using a plain crystal. It is only detectable when using the "FAST" 20 ohm outputs. The Eval and Edge boards both have a lot of poured copper surrounding the Prop2.
You might even be able to get it to work with a breakout for PSRAM using your expansion connector but it'd be a gamble and you'd want to try to route the signals with similar impedance and lengths to some degree. I made a 64MB PSRAM breakout for the P2 EVAL which ended up working with Ada's NeoYume, but the margin was rather close IIRC. You have available a perfect number of P2 IO signals (20) for two banks and you could choose to operate two independent 8 bit 16MB banks, or 2x32 MB banks at 16 bits if you have two chip selects and two clock signals (one CLK each per 8 bits of data width, one CS each per 32MB). That's how I did my 64MB wiring.
From a signal integrity viewpoint not sure it'd be good to have the connector AND PSRAM on the same board with the connector pins becoming unterminated stubs on clock and data lines but maybe you can get away with it if you try it like that. I found PSRAM reasonably forgiving with the stubs on my own board when only 32MB was fitted (although they were very short). Or perhaps you could make two layout variants of your board, one with PSRAM fitted and no connector wired in, and one with that wide connector but no PSRAM and produce both PCBs at the same time, essentially like Parallax did with the two P2Edge variants (P2-EC32MB vs regular P2 Edge).
The traces between the P2 and the bypass capacitors look way too long. Too much parasitic inductance. I assume that designing for digital logic is similar to designing power converters.
https://epc-co.com/epc/Portals/0/epc/documents/papers/Optimizing PCB Layout with eGaN FETs.pdf
@Rayman do you know of a good program to test max speed that doesn't need PSRAM? I'll test my 2 layer board.
Chip's code for programming the EEPROM chip is quite good (on those few pins). It uses the streamer and goes about as quick as possible at RCFAST sysclock. It wouldn't take much to add a clock setter on the front of that and run the code much faster. Even without any compensation, the highest reliable speed it can reach should be a good test of the board layout.
@SaucySoliton See post #20, there are now very short run caps on bottom of board, if needed.
@rogloh Your 64 MB layout had two CS and two clocks, right? One CS for each 16-bit bank. Clocks for each 8-bit half bus. Guess that lets you address as four independent 8-bit banks.
Rayman,
Are you planning on using DDR or SDR parts?
I ask because DDR has potential for operating right at sysclock frequency whereas SDR doesn't. This in turn means integrity demands for DDR is much higher but I believe is worth pursuing when integrating into a single board layout like this.
On the flip side, the number of banked ICs impacts speed. So top speeds will only be possible with one or two banked packages. The DDR plans I have would require a minimum of double width in parallel to preset appropriate DDR clock skew. So, for 8-bit parts, two wide makes a 16-bit pair on the one clock pin.
SDR does provide a lot more flexibility, as per Roger's comments. The extra effort in DDR would only be worth it if sysclock/1 speed could be achieved.