Smart pin count mode %01100 w/o using adjacent pin
JRoark Posts: 1,204
in Propeller 2
I'm probably missing something simple here. I want to configure a smart pin to count rising edges. Easy, right? BUT I dont want to waste an adjacent pin. The manual says:
**Count A-Input Positive Edges When B-Input Is High (%01100)** ● X[31:0] establishes a measurement period in clock cycles. ● If zero is used for the period, the measurement operation will not be periodic, but continuous, like a totalizer, and the current 32-bit high count can always be read via RDPIN / RQPIN. ● If a non-zero value is used for the period, events will be counted for that many clock cycles and then the result will be placed in Z, while the accumulator will be set to the 0/1 value that would have otherwise been added into it, beginning a new measurement. This way, all events get counted across measurements. At the end of each period, IN will be raised and RDPIN / RQPIN can be used to retrieve the 32-bit measurement. ● During reset (DIR=0), IN is low and Z is set to the adder value (0/1).
This is exactly the functionality I want, BUT, I don't want/need that adjacent pin. The B-Input does nothing for me. I need an always-on totalizer. If it gets a pulse, it increments Z, regardless of anything the adjacent B-pin is doing. How do I do this?
You want the
And, I'm happy to report the dunce cap still fits!
Count A-Input Rises (%01110) looks like it's what I should have been using.
Mode %01100 is what you'd use for performing Sinc1 filtering for a bitstream ADC. SmartA input is the clock pin and SmartB input is the bitstream pin.
Of course, there is the Sinc2 and Sinc3 filters in the other specialised smartpin modes so probably this one will never get used.
Of course, you can reset the count like this if needed:
Many thanks to all. @Wuerfel_21 and I posted simultaneously. Happy to report its working nicely using @JonnyMac / Ada's approach.
FWIW, my function generator goes up to 25 mhz, and the P2 at 160mhz has no problem keeping up with that. Pretty cool to just "set and forget" and let the hardware deal with counting. Screen cap at 25 mhz square wave input swinging rail to rail with a 1 sec sampling period:
@evanh I have to admit I'm not following you. The manual says the ADC stuff sits at %11000 and %11001. Your statements are always carefully measured, so I'm trying to figure-out what I missed.
ADC Sample/Filter/Capture, Internally Clocked (%11000)
ADC Sample/Filter/Capture, Externally Clocked (%11001)
Just FYI, for low frequencies, I think the reciprocal counter mode is nice.
Gotta save that trick for my next project. 👍
Those are the specialised Sinc filters for handling Sigma-Delta ADC bitstreams. They each optionally perform Sinc2 or Sinc3 filtering, but not Sinc1.
Mode %01100 isn't explicitly an ADC mode. It just happens to be how a Sinc1 filter works. So it's the Sinc1 version of the externally clocked mode %11001 above.
Mode %01111 (with Y=0) would be the Sinc1 version of mode %11000 above.
BTW: Sigma-Delta bitstreams, both from an ADC and to a DAC, are a form of PDM (Pulse Density Modulation) that I've been raving about elsewhere. They'll get called a bitstream because of the matching synchronous clock that goes alongside.