Complete cycle-correct emulation of CPU with external bus
Andrey Demenev
Posts: 377
in Propeller 2
Hi everyone!
It's been over 10 years since I did something with the Propeller. I just got tired waiting for Prop2, then life stuff kicked in, so I could not do any electronics at all. But I guess you cannot just throw away the Propeller passion 
So I am thinking about a good project to learn the ins and outs of Prop2, and I have this idea of a CPU emulator that not only executes the instructions correctly, but also has a proper electrical bus with correct timing that would allow connecting external hardware. Possibly Z80, 6502 or 6800.
Anyone knows if such a project exists for P2?
Comments
No, does not exist yet. I have created 68000, Z80 and SPC700 cores, but those have instruction-level timing at best (or no timing at all for the 68000). Pratically all the peripherals you could realistically want for an 80s CPU can also be emulated inside the P2. But external bus emulation should be possible for the slower 8-bit CPUs.
6502 emulator by macca, while not doing this as it is now, can be upgraded to do this as there is still a place in LUT RAM, a lot of time, and its structure allows such upgrade.
Thanks, I'll look into it
While waiting for the propeller board to arrive, I am trying to outline the project and understand what I would need. So it looks like 6502 would be a good starting point, as it is least complicated in terms of both instructions and the bus. Well, there is BCD, but let's leave it for now
To debug the electrical bus, I would need some means of analyzing what's going on there. Unfortunately, I am living out of my home now, finances are pretty limited, and I do not have access to an oscilloscope, and even obtaining electronic components is kinda troublesome. I was thinking about making some basic logic analyzer out of 74 logic which I can get here. The idea is to latch the bus state into registers, and then shift the bits out, receive them with a USB to serial converted and visualize on a computer. I think I could run the Prop at extremely low clock frequency, so the serial transmission rate is within usable range , and the bus state can be transmitted on each prop clock
Depending on your budget, there are very low cost HS-USB parallel logic analysers like this
https://www.aliexpress.com/item/32896748758.html
or this, in a case
https://www.aliexpress.com/item/1005001417581550.html
Those use a Cypress HS-USB parallel chip (or a clone) and sample at up to 24MHz, so you would not need to slow the Prop much ?
and I find this
https://community.infineon.com/t5/Knowledge-Base-Articles/Cypress-EZ-USB-FX2LP-based-Logic-Analyzer-using-Open-Source-sigrok-PulseView/ta-p/252866
Sync to the Prop clock is a good idea, or vice versa.
I find this
https://sigrok.org/wiki/Lcsoft_Mini_Board
that mentions a 24MHz xtal, so you could do a simple HW mod to add a 1GU04 / 2GU04 buffer to the CY7C68013A crystal, to get a buffered version you could feed into P2 XI, replacing the 20MHz xtal.
That 'same clock' keeps the P2 and capture clocks phase locked, and some small loading (could even be the P2 Xtal Caps) adjust could nudge the phase a little, if you find sampling point issues.
Thanks. I tend to overcomplicate things
I think I could use STM32 blue pill - it's fast and has enough pins
Speaking of STM and low speed I got one of those DSO138 units that worked ok.
I now use a PropScope.
Mike
It should probably be possible to use one cog of P2 to monitor the pins, I think!?!
Don't You want to tackle the 6809? A P2 coco3 emulator with OS9 would be the perfect match....
I invested some time, but my porting attempt in C was too slow. https://forums.parallax.com/discussion/174794/towards-os9-operating-system-on-p2/p1
No need for any hardware. Visual 6502 is a transistor-level simulator that can run 6502 programs using URLs containing 6502 opcodes.
Visual 6502
http://www.visual6502.org/JSSim/
Advanced version is more useful:
http://www.visual6502.org/JSSim/expert.html
Example URL:
http://visual6502.org/JSSim/expert.html?graphics=f&loglevel=-1&steps=24&r=2303&a=2303&d=38b0fea9ffeae8&nmi0=6&logmore=cycle,ab,db,rw,Fetch,pc,Execute,State,nmi,D1x1
copied from here:
http://forum.6502.org/viewtopic.php?p=16141#p16141
User help:
https://web.archive.org/web/20200201082442/http://visual6502.org/wiki/index.php?title=JssimUserHelp
Wiki:
https://web.archive.org/web/20210115205040/http://visual6502.org/wiki/index.php?title=Special:AllPages
Github:
https://github.com/trebonian/visual6502
Node names and numbers can be found in:
https://github.com/trebonian/visual6502/blob/master/nodenames.js
C port:
https://github.com/mist64/perfect6502
Yes, that would be perfect. I am not sure yet if that can be done though
How is that going to aid in finding out what the propeller is outputting to the bus?
It can be done, but comes with caveats.
It consumes a COG and requires the P2 to be 'up and running'.
It also imposes a CLK max, which becomes a conflict
if we start at fastest UARTS that's roughly 1MBytes/sec so you can sample 1M/s, but you need 12M osc to send, so the sample and clk speeds cannot be the same.
The HS-USB modules based on CY7C68013A etc are 24x faster than that.
Yes, I was thinking about it. Obviously an additional cog is required, even maybe 2 - the other one for bus-attached memory emulation. The bus state can be sampled into a buffer, and at the end of each machine cycle the simulation cog would wait for a signal that is emitted when serial transmission is complete. Not exactly real time and comes with a cost of additional instruction per machine cycle, but can be enough at the early stages of development