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P2 Edge Rev D at 19.2 - Page 2 — Parallax Forums

P2 Edge Rev D at 19.2

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  • @"frank freedman" said:
    This may become a bit of a problem. Parallax, who supplies these for you? The usual suspects are showing > 12 weeks lead time for these oscillators. Need to find a source for a few. Digi-Key, October 10 this year. Mouser September

    One other option- look for 2016 package size of 1.8V oscillator.

    The footprint on the Edge modules will accept either 2520 or 2016 (2.5 x 2.0mm or 2.0 x 1.6 mm)

  • jmgjmg Posts: 15,173

    @"frank freedman" said:
    .. The usual suspects are showing > 12 weeks lead time for these oscillators. Need to find a source for a few. Digi-Key, October 10 this year. Mouser September

    For 19.2MHz TCXO :
    Mouser show 74 in 2520 package, and more in 2016 case size
    Digikey show 600+ in 2520 and a few thousand in 2016 case.

  • evanhevanh Posts: 15,913
    edited 2023-04-18 01:36

    @iseries said:
    ...
    Now I compiled the program with the correct frequency and everything is right on.

    I guess it's not a pain to switch frequencies.

    There is a small penalty of increased jitter with the higher DIVD divider values. I did some testing not long ago to measure the impact and got what I thought was a relatively linear graph of divider value to jitter magnitude when above 200 MHz for the PLL's VCO frequency (pre-DIVP). Below 200 MHz there is a larger jitter factor that has greater impact. It's all pretty small above 100 MHz though. Which is why Chip made 100 MHz the lower limit when setting the PLL's VCO frequency.

    Sorry, I never gave the results a specific value. My knowledge of the correct maths, terms and practices is limited.

    EDIT: Here's some testing - https://forums.parallax.com/discussion/comment/1546525/#Comment_1546525

  • @jmg said:

    @"frank freedman" said:
    .. The usual suspects are showing > 12 weeks lead time for these oscillators. Need to find a source for a few. Digi-Key, October 10 this year. Mouser September

    For 19.2MHz TCXO :
    Mouser show 74 in 2520 package, and more in 2016 case size
    Digikey show 600+ in 2520 and a few thousand in 2016 case.

    Odd. > @jmg said:

    @"frank freedman" said:
    .. The usual suspects are showing > 12 weeks lead time for these oscillators. Need to find a source for a few. Digi-Key, October 10 this year. Mouser September

    For 19.2MHz TCXO :
    Mouser show 74 in 2520 package, and more in 2016 case size
    Digikey show 600+ in 2520 and a few thousand in 2016 case.

    Wonder what I missed. Just dropped the part number @VonSzarvas listed. Did you keep the Mouser or digikey part number?

    thanks

  • jmgjmg Posts: 15,173
    edited 2023-04-18 09:46

    @"frank freedman" said:

    @jmg said:
    For 19.2MHz TCXO :
    Mouser show 74 in 2520 package, and more in 2016 case size
    Digikey show 600+ in 2520 and a few thousand in 2016 case.

    Wonder what I missed. Just dropped the part number @VonSzarvas listed. Did you keep the Mouser or digikey part number?

    I just did a generic search for TCXO 19.2 MHz Oscillators and then selected case size.
    These things are widely multi-sourced.

    Addit: I'm unclear if you want 19.2Mhz Clipped sine TCXO as discussed for rev D, or a TCXO for older boards (20MHz?)

    I notice the newish ECS-TXO-2520-33-200-AN is now well stocked, that's a 20.00MHz TCXO with CMOS out, so it does not need the clipped sine amplifier of RevD Edge.
    ( ppm is not quite as good as 19.2MHz GPS TCXO, but a lot better than a generic crystal oscillator)
    https://octopart.com/search?q=ECS-TXO-2520-33-200-AN&currency=USD&specs=0

    Addit2: I see ECS also have sibling parts like
    ECS-TXO-25CSMV = Clipped sine, claims 20,32,40MHz
    ECS-TXO-25CSMV-AC = clipped sine, AC = "uses Analog Compensation which is ideal for stability critical applications", I think that means no digitial correction jumps, but exists only in 26MHz (GPS)
    ECS-TXO-2520MV = CMOS, gives Phase Jitter (12 KHz ~ 20 MHz) @ 50 MHz typ254 fs part codes for 10,12,16,20, 24,25,32,40,50MHz

    Addit2: I see recent news of a ECS-TXO-20CSMV4- series.
    https://ecsxtal.com/ecs-electronic-component-new-product-announcements/ecs-txo-20csmv4-analog-compensated-clipped-sine-wave-multivolt-tcxo/
    2016 package with the Analog compensation, released in 26,32,38.4,39MHz

    @evanh said:
    There is a small penalty of increased jitter with the higher DIVD divider values. ..
    EDIT: Here's some testing - https://forums.parallax.com/discussion/comment/1546525/#Comment_1546525

    I wonder how much this matters to most use cases, and would a higher XIN allow an even higher PFD than 20MHz be of any use ?

  • Was going to order the 20MHz part and switch them using an Zephyrtronics air rework station. At a couple bucks each, made this a really good bargain price for the boards without worry of which board was which. As long as the fit works and the CMOS out is compatible with the P2, then that works for me. So far, only managed to kill one P2 edge using a stepper controller board. Not sure why. So cheap extras on hand seemed like a good idea.

  • jmgjmg Posts: 15,173

    @"frank freedman" said:
    Was going to order the 20MHz part and switch them using an Zephyrtronics air rework station. At a couple bucks each, made this a really good bargain price for the boards without worry of which board was which.
    As long as the fit works and the CMOS out is compatible with the P2, then that works for me.

    CMOS should simply over-drive the AC coupled clipped sine buffers.
    If you use some ECS-TXO, be interested to know the ppm errors they have, typically.

  • @evanh,

    I thought the jitter was reduced by the new TXCO part used instead of the crystal.

    Mike

  • evanhevanh Posts: 15,913
    edited 2023-04-19 16:35

    @iseries said:
    @evanh,

    I thought the jitter was reduced by the new TXCO part used instead of the crystal.

    Yep. There is many sources of jitter. I've listed only two that I was measuring - The DIVD associated one and the PLL's natural VCO jitter. Larger DIVDs produce larger jitter. The DIVD component pokes above the increasingly cleaner natural VCO jitter as the VCO frequency is increased.

    The external oscillator module was used to avoid a flaw (Missing Schmitt buffer/inverter) in the XI pin. The flaw could induce extra toggles of the clock input and this would create instability in the PLL which showed up as jitter.

  • evanhevanh Posts: 15,913
    edited 2023-04-19 16:53

    @jmg said:

    @evanh said:
    There is a small penalty of increased jitter with the higher DIVD divider values. ..
    EDIT: Here's some testing - https://forums.parallax.com/discussion/comment/1546525/#Comment_1546525

    I wonder how much this matters to most use cases, and would a higher XIN allow an even higher PFD than 20MHz be of any use ?

    It's small for sure. I had my scope maxed out to see anything. I don't know how to quantify it though, sorry.

    EDIT: Oh, I just worked out one point - DIVD is directly after XI input. So it divides down the 20 MHz before the Phase Frequency Detector.

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