Wiznet W5100/W5200 vs W6100

msrobots · 2023-04-05 05:22

Since @ke4pjw, aka Terry build that nice board and send it to me I try to adapt my socket driver for W5100/W5200 to the W6100.

Gosh guys ad gals, it is complicated. On the first glance they look pretty alike from the programming standpoint, but hell no, the devil lurks in the details.

While the 5xxx chips give you a memory map for the registers and you basically calculate one address in that memory to access that common or socket register alike
socket * SOCKET_REG_SIZE + SOCKET_BASE_ADDRESS + register
the W610 needs you to address 4 different kinds of memory with 0 based offsets.

Just venting after miss reading the datasheet for 2 days now...

getting there,

Mike

ke4pjw · 2023-04-05 06:00

I had the exact opposite experience! I couldn't make heads nor tails of the W5100/5200 datasheet. It was my primary reason for choosing the W6100. I just wrote my code based on the pseudo code in the datasheet. It all just made sense to me. Here are all of the block selections.

' Block Selection (BS)
IDM_BSR_Common_Register = %000_00_000
IDM_BSR_Socket0_Register = %000_01_000
IDM_BSR_Socket0_TX_Buffer = %000_10_000
IDM_BSR_Socket0_RX_Buffer = %000_11_000
IDM_BSR_Socket1_Register = %001_01_000
IDM_BSR_Socket1_TX_Buffer = %001_10_000
IDM_BSR_Socket1_RX_Buffer = %001_11_000
IDM_BSR_Socket2_Register = %010_01_000
IDM_BSR_Socket2_TX_Buffer = %010_10_000
IDM_BSR_Socket2_RX_Buffer = %010_11_000
IDM_BSR_Socket3_Register = %011_01_000
IDM_BSR_Socket3_TX_Buffer = %011_10_000
IDM_BSR_Socket3_RX_Buffer = %011_11_000
IDM_BSR_Socket4_Register = %100_01_000
IDM_BSR_Socket4_TX_Buffer = %100_10_000
IDM_BSR_Socket4_RX_Buffer = %100_11_000
IDM_BSR_Socket5_Register = %101_01_000
IDM_BSR_Socket5_TX_Buffer = %101_10_000
IDM_BSR_Socket5_RX_Buffer = %101_11_000
IDM_BSR_Socket6_Register = %110_01_000
IDM_BSR_Socket6_TX_Buffer = %110_10_000
IDM_BSR_Socket6_RX_Buffer = %110_11_000
IDM_BSR_Socket7_Register = %111_01_000
IDM_BSR_Socket7_TX_Buffer = %111_10_000
IDM_BSR_Socket7_RX_Buffer = %111_11_000

When I want to read a register, I just pass which address register I want to read, the block it resides in, the number of bytes to return and a pointer to where I want those bytes written to.

PUB readreg(REGISTER,BS,BLEN,RB) : r | i , LADDRL, LADDRH, tmpdata, tmpptr, datapin
repeat until locktry(EthernetLock) < 0
if SPIMODE == true
    pinl(CSn)
    r := 0
    spi.write(SPI.MSBFIRST,REGISTER,16) ' Set the address registers
    spi.write(SPI.MSBFIRST,BS,8) ' Set the BS register
    i := 0
    repeat BLEN
       byte[RB][i] := SPI.read(SPI.MSBFIRST,8)
       i++
    r := byte[RB][i-1]
    pinh(CSn)
    lockrel(ethernetlock)
    return r
<snipped the parallel mode for brevity>

Sorry it is giving you fits! Over the past year I have became very familiar with the chip. If you have questions, let me know! I will do my best to help.

msrobots · 2023-04-05 06:23

Yes, thank you I studied your code and the datasheet and then it clicked and I found out why I was running against a wall with just fiddling with my W5100 and W5200 drivers.

"Those who can read have clearly a advantage"

I am getting there. Your second board arrived and also works fine with SPI or PARALLEL. Love them.

Mike

Wiznet W5100/W5200 vs W6100

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