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XI = 4 MHz ? — Parallax Forums

XI = 4 MHz ?

Could external clock input to XI be as low as 4 MHz?


  • evanhevanh Posts: 14,110
    edited 2023-02-17 13:49

    With PLL off, yes XI can go right down to zero Hertz.
    With PLL on, minimum XI frequency would be about 100 kHz (100 MHz VCO / 1024 multiplier). But then DIVD and MUL can only do x1000(+) to get VCO to achieve stable 100 MHz, leaving only DIVP (1..30) divider as adjustable.

    PS: The PLL's VCO can go lower but below about 60 MHz its instability becomes quite notable. Chip has designated 100 MHz as recommended minimum. In reality 200 MHz is measurably more stable than 100 MHz.

    PPS: Although I didn't post any examples at 100 MHz, I measured it during the jitter testing at different DIVD dividers - The improved stability at higher frequencies is the reason I chose to work around 250 MHz. I wanted as clean as possible to detect any differences from different MUL and DIVD settings.

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