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DIY Chips - ~$10k — Parallax Forums

DIY Chips - ~$10k

Has anyone else seen this? You can design your own chip for fab. I’m still digesting it all, but this looks like something neat. 100 pieces of QFN with custom internals is about $10k. My reason for posting this is to see if Parallax knows about this path for further editions of the P2. There is a 130 and 90 nm process node with both analog and digital capability.

https://www.skywatertechnology.com/cmos/

Comments

  • jmgjmg Posts: 14,994
    edited 2023-01-05 21:36

    @JRoark said:
    Has anyone else seen this? You can design your own chip for fab. I’m still digesting it all, but this looks like something neat. 100 pieces of QFN with custom internals is about $10k. My reason for posting this is to see if Parallax knows about this path for further editions of the P2. There is a 130 and 90 nm process node with both analog and digital capability.

    https://www.skywatertechnology.com/cmos/

    Interesting approach.
    Very much a hard-wired RISC-V with user custom logic area, of 10 sq mm, so much smaller than P2 die.
    It has a modest user area, and modest RAM at 3k bytes, fixed to execute RISC V from external QSPI Flash.

    The support peripherals are very much smallest-die focused : No FIFO on UART, and 2 very simple timer/counters, no ADC or DAC on the hard platform.

    No boot rom, the default is to boot from FLASH:0000 and at SysCLK on external CMOS clock pin.
    There is a housekeeping SPI bus, that allows programming access of the QSPI flash part, and gives debug and PLL/DCO access.

    A SPI-USB bridge part would make this more usable, and they look to have an Eval Board that can take the standard pinout carriers. Wonder what that uses for USB connect ?

    Too small for a P2 road map part, but I wonder if a P1V could tile into that 10 sq mm ?
    It's unclear how you mix-in hardened IP like tight mutliport RAM blocks, which would give best density on COG and HUB memory.

    Their example projects give some idea what can fit

    sermo-soc - looks to add

    * Closed Loop PID Controller (x4)
    * PWM Generator (x4)
    * Delta Sigma Input (Decimation Filters such as CIC Filters) (x8)
    * Direct Digital Synthesizers (DDS) for Generating Sinusoids 
    

    Riscduino is more MCU like package - the USB host is interesting.

    * RISC-V core  
    * 4KB SRAM for data memory
    * Pin Compatible to arudino uno
    * Quad SPI Master
    * UART with 16Byte FIFO
    * USB 1.1 Host
    * I2C Master
    * 6 Channel ADC
    * 6 PWM
    
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