Perpetual reset
JRoark
Posts: 1,215
in Propeller 2
Is there any harm in keeping a P2 in a perpetual reset condition? There would be an external clipped sine osc still running on the XI input and some of the pins would still be driven gently by external devices (SPI, memory).
FWIW I’m trying to go as low as possible on current draw until an external signal releases the reset line and allows the P2 to boot.
Comments
Why would keeping a micro in a reset condition do any harm to it ? Reset is a very valid state. I have never ever seen a datsheet that even remotely suggests that keeping a micro in reset state can do anything harmful to it.
On the other hand, being in a reset state does not necessarily mean a micro is in the lowest possible power consumption mode.
Bear in mind however that being in reset is different from being powered off and that could be harmful if there are signals already applied to the micro being powered off (but I think you meant a valid reset under power on condition).
It’s an interesting question…
How low power a state is reset?
Is it the lowest ?
I’m not sure reset was designed to be a lowest power state, but maybe it is…
Maybe switching to internal clock, setting all I/Os to either high or low (depending on what they are connected to) to prevent leakage current via the I/O pin "virtual" body diodes/etc.., and having all cogs go to sleep. Anything else...? That might get a lower power state than just holding reset.
An interesting experiment afoot !
The points raised are all quite good. They got me thinking.
It is true: I dont actually know if the reset condition IS the P2’s lowest power state! I simply assumed that it would be since there is nothing else going on in the chip that I’m aware of. From following the evolution of the P2 I recall the substantial power reductions that came with Chip’s/OnSemi’s clock-gating efforts, and I extrapolated from that. I may be milking without a bucket, so I suppose I’ll have to knuckle-under and do the measurement when I return home late in the week. I’ll post some numbers for the benefit of those who may travel this path later.
It has to be lowest. I suspect even the oscillators stop, both external and internal.
I hope you are correct, and this was my thought as well. The external osc in this case will keep running at the cost of (maybe) a dozen (?) microamps. Its basically not even a consideration in my power calc at this stage. But that big ol’ P2 running at 320 mhz and chewing-up >350 mA is a concern when I’m trying to get >90 days on a small lead/acid rechargable… so… yeah. 😎
How much power loss would expect in the regulators for the P2?
If you can shut them off when the P2 is 'stalled' you might save more power there and not need to hold the P2 in reset.
Other factors to consider are how much power it will take to
1. continually run the other circuit that will release reset
2. boot the big ol' P2 into a usable state upon release from reset; and
3. save any state that needs to be maintained to Flash or SD before retriggering the reset circuit
versus
and, of course, the expected trigger rate will need to be taken into account. Once a day would probably skew toward the former, while once an hour might skew toward the latter.
I remember that someone compared power consumption of a cog sitting at a WAIT condition (like you would on the P1) to a cog sitting in a busy loop waiting for an interrupt condition, but I don't recall the outcome.
I compared a stopped cog against a waiting cog and the waiting cog appeared to use less. The difference was tiny.
RCSLOW had the biggest impact. It would be interesting to see if reset would be less than RCSLOW.
I would think that setting the clock mode to XIN and disabling the external oscillator would draw less power than running on RCSLOW. But you have to try out if it really makes a difference and if it's worth making the external circuit more complicated.
I'm testing a bare bones P2 board at the moment, so have been able to run some quick tests with OzPropDev's cool multimeter
At 3.3v VIO and 1.8v VDD nominal supplies,
In RESET - VDD current is around 22~25uA
In RCSLOW - VDD current is around 47uA
What's interesting is I can keep interacting with Taqoz down to around 1.30v VDD*, and down there,
RESET VDD current is around 17uA
RCSLOW VDD current is around 32 uA
I didn't realise the P2 could operate this low, it opens up some interesting possibilities
@Tubular WOW! Thank you for that!
That is basically flea power.
In further testing, it looks like the lowest VDD can dip to, without upsetting internal taqoz operation is around 0.82V.
I/O cuts out around 1.30v, but dipping VDD down to 0.82V for a while, then bringing it back above 1.35V restores Taqoz interaction once again.
In another test, I was able to boot the P2 and run Taqoz OK by setting both VIO and VDD to 1.5v, and I have a red led dimly blinking.
Current consumption is around 39uA without or 45uA with the dimly blinking red LED.
So perhaps it is possible to operate P2 from a single AA alkaline battery for around 3 years of controlled (rcslow) standby
In all this testing, the flash chip is yet to be installed. It makes me think I should get some of the flash chips in that operate down to the lower voltages
Tubular, you are Da Man! Thanks for doing this testing.
Interesting numbers. How does that vary with temperature ?
From a total system power viewpoint, RCSLOW could be useful as it allows pins to be defined, in RESET all pins float, so pullups/pulldowns would be needed on every connected pin that has a CMOS type load.
I did do a quick freeze spray while operating at 1.3v, and saw the VDD current (In RESET) down as low as 16uA.
I suspect lots of this has to do with RCSLOW oscillator which has quite a temperature coefficient (RCFAST was very steady by comparison)
Yes I agree I think RCSLOW is going to be very useful.
This sounds really useful Tubular. Have been considering which micro to use in an upcoming audio project for my car and was somewhat worried about possibly tens of mA of extra sleep current in the P2 draining the battery in addition to its other existing loads but your result shows it could basically become negligible if it could be paired with low quiescent current regulators and put into RCslow mode to sleep.
Only thing that worries me is this:
So for RCslow to work at the low currents you do need to lower the VIO supply...?
It was only when lowering VDD all the way down to 1.3v that I dropped the 3v3 rail a bit. It was showing about 3 or 4 mA drawn. So if you stick to 3v3 and 1v8 you'd be fine.
I'll check 1.5v later (of interest as a single alkaline cell, or perhaps dual cells to get both VDD and VIO)
There's some low iq switchers like TPSM82822 that only take 4uA that might work well here
For certain, as you lower VDD then the max VIO will also need reducing, else the IO fets won't switch properly.
Might be some info in the Eval RevA guide or design notes; that board included variable VDD and VIO supplies for such experiments.
If this could work with a flash chip installed, would be very interesting.
Sounds like could have P2 control it's own 3.0 V VIO, turn it off when sleeping, with 1.5 supplied by Schottky diode or some way...
Maybe P2 could turn off power to flash when sleeping too...
Update on the VDD info--- All I could find was the upper specs (VDD 2.2V max, VIO 4V max).
An interesting question for Chip at the next P2LF, if he recalls any abs lower limits (and/or tested limits). He might also know what the minimum delta between VIO and VDD needs to be.
The internal RCFAST/RCSLOW need VIO supplied on V2831. Similar for the reset circuits, they need VIO supplied on V6063.
EDIT: Corrected V2831 pin label.
@evanh i meant that vio would be applied by battery through diode when 3.0 volts was removed.
Today i had a quick look at the P2 pin drive impedance at reduced voltages
VIO=VDD=1.8v - Pin drive impedance about 50 ohms
VIO=VDD=1.5v - Pin drive impedance about 100 ohms
Thats a fair bit lower than I was expecting.
Yeah that's not really high. Maybe still sufficient to boot from flash at lower frequencies without timing out?
Some more data points this morning
While we're at it I had a quick look at DAC output at low supply voltages, with a view to later trying VGA output.
Because the supply voltage is now just 1.5/1.65/1.8v, there's little point using the 75 ohm DAC , we used the 124 ohm dac instead.
The following peak voltages were observed, driving the 124 R dac into 75 ohm load:-
1.80v VDD & VIO supply = 0.68 volts
1.65v VDD & VIO supply = 0.62 volts
1.50v VDD & VIO supply = 0.55 volts
While these values are short of the 1.0v peak desired for video, they'd just result in a slightly dimmer display. There's a separate question of whether monitors would respond to 1.5~1.8v H and V sync pulses. Unfortunately we don't have time for this rabbit hole just right at the moment