Smart Pin Documentation, Count A-Input Highs
ManAtWork
Posts: 2,178
I'm trying to implement a PWM input by using the smart pin mode "Count A-input highs" (%01111 AND !Y[0]). It works to some degree, at least I get higher numbers for higher duty cycles. But I expected that I can synchronize the counting periods set with X to the fixed edge of the input signal by resetting the smart pin (DIR=0). However, this doesn't work. DIR=0 resets the counter value (Z) but not the timer (X=measurement period in clock cycles).
How can I synchronize/reset the period timer? Does any wxpin re-start the timer? Or do I have to set the period to zero (non-periodic counting mode) and then back to a finite period?
Parallax, could you please, please finish the documentation for the P2 ?! The current hardware manual only contains very sparse information. There are many counter modes (%01100 to %10111) with some basic behaviour documented. But there are no intended purposes or examples given. So it takes some time to find out which mode fits best a particular application. And we need to find out by trial and error how to set it up.
Some of the enthusiasts here may find it interesting to solve puzzles and to do research. But I think the average application engineer doesn't have the time for that.
Comments
Hmm, no, that doesn't work. I've just tried some differnt things like clearing and re-setting the X register or the smartpin mode. But none of them seem to work. Even
wxpin #1,#pinPwmIn wxpin pwmPeriod,#pinPwmInhas no effect. My idea was that wxpin #1 should cause an immediate wrap-around of the timer and the following wxpin pwmPeriod should the start at a defined value of 0 or 1.
Remember the trick with repository mode? You can change the internal register in that mode. I'm not sure if it will have any effect on the PWM mode though but it might be worth trying.
Yeah, the counter modes are cryptic alright. I've tried relabelling the names in the past just to categorise them all.
That particular mode is Sinc1 PDM input. Works with the ADC bitstream. I believe mode %01100 (Count A-input positive edges when B-input is high) can also serve as Sinc1 PDM for externally clocked bitstreams. But I digress.
For PWM, could use a pulse timer. Same as what's used for the model "servo" community. This method just assumes a pulse period without being measured. Only the pulse length is measured. Mode %10001 (Time A-input high states) should work for this approach. I'd start with this for simplicity.
The more sophisticated modes work in tandem so need two smartpins for each PWM input. Modes %10101 and %10110 paired will precisely measure the average PWM via a high time of multiple pulses over total time of the same multiple pulses within a specified measuring duration.
EDIT: Dunno what happens at 0% and 100%, sorry. Hopefully mode %10110 will return the X duration in Z result when pin is solid high and zero in Z result when pin is solid low.
As I generate the timing by myself I think I don't need two smart pins to measure both high and low time. But I like the idea to measure the time span between the rising and falling edge instead of the high time itself (counting 1-states). That would also solve the synchonisation problem as IN would be raised as soon as the second edge is detected and I could re-arm the timer for the next cycle with a software ISR.
My application is a dual slope ADC converter which has 3 phases:
1. discharge integrator
2. integrate input signal (fixed time, variable slope)
3. de-integrate reference signal (variable time, fixed slope)
I need to measure the pulse width of the comperator during phase 3. The rising (A) edge has always a fixed timing (period = 3 times the phase duration). The falling (B) edge occurs at 0..100% of the 3rd phase. So what mode would be the best for that? I could route the B input to the inverted A signal so I can time a single pin using the A-edge to B-edge feature.
Ah, not an ordinary PWM then - 0% and 100% still have a pulse cycle. That makes it easier, mode %10001 is good to go then. Won't need the special handling for non-pulses.
Yeah, that distinction is tricky to keep in mind. I've been labelling the former a "timer" counter and the latter an "accumulate" counter.
EDIT: Here's what I have. Bit of a rewrite from prior attempts:
%01011_0, P_QUADRATURE ' Count: A-B quadrature encoder %01100_0, P_REG_UP ' Count: A clock up, B enable %01101_0, P_REG_UP_DOWN ' Count: A clock, B direction %01110_0, P_COUNT_RISES Y=%0 ' Count: A clock up Y=%1 ' Count: A clock up, B clock down %01111_0, P_COUNT_HIGHS Y=%0 ' Accum: A up Y=%1 ' Accum: A up, B down %10000_0, P_STATE_TICKS ' Time: of prior level duration %10001_0, P_HIGH_TICKS ' Time: of prior high duration %10010_0, P_EVENTS_TICKS Y=%0xx ' Time: of X number of highs/pulses/steps Y=%1xx ' Time: since latest high/rise/edge, with X timeout %10011_0, P_PERIODS_TICKS ' Time: of X number of A-B cycles %10100_0, P_PERIODS_HIGHS ' Accum: A up, during X number of A-B cycles %10101_0, P_COUNTER_TICKS ' Time: of complete A-B cycles, for at least X duration %10110_0, P_COUNTER_HIGHS ' Accum: A up, during complete A-B cycles, for at least X duration %10111_0, P_COUNTER_PERIODS ' Count: of complete A-B cycles, for at least X duration KEY ========= Time : Z result (RDPIN) duration of event or events, measured in sysclock ticks Accum : Z result (RDPIN) input gated time, measured in sysclock ticks Count : Z result (RDPIN) counted events Rise : a low-to-high level change Fall : a high-to-low level change Edge : a low-to-high or high-to-low level change Pulse : a rise-to-fall high level Step : a rise-to-fall high level or fall-to-rise low level Cycle : a rise-to-rise high-low cycleThis is a nice List!
Thanks for sharing!!!
Thanks for the kudos. Yeah, it certainly had me reading Chip's descriptions over and over. Revisiting a few times over a few years.