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Looking for P1V for the DE10-Lite — Parallax Forums

Looking for P1V for the DE10-Lite

blittled2blittled2 Posts: 25
edited 2022-02-23 02:49 in Propeller 1

I was wondering if anyone ported over the P1V files to a DE10-Lite and if you are willing to share your project? I want to learn more about FPGAs and I feel using the Propeller, which I have used, would be a good base to work from. I do have a DE0-Nano as well but the DE10-Lite has more memory and flexibility leading to more interesting projects. Thanks.

Comments

  • iseriesiseries Posts: 1,492

    I too wanted to learn about FPGAs a while back and decided to get this board: DE10-Nano Kit.

    The unit came with their HPS processor and linux os.

    The software to program it is massive and is not the easiest to figure out.

    Someday I want to build an HDMI driver with this kit so I can drive a monitor and display data from the p1 or p2.

    Having too much fun just programming the P2.

    Mike

  • RaymanRayman Posts: 14,632

    Looks like @ozpropdev did it before: https://forums.parallax.com/discussion/165551/new-de10-lite-max10-fpga-board-perfect-forr-p1v-experiments/p1

    Might ask him for it...

    Or, I imagine wouldn't be too hard to make it work. Figuring out the constraints file is most of the work, I think.

  • blittled2blittled2 Posts: 25

    Thanks Rayman, that was the post that got me to dig out the DE10-Lite in the first place. I'm going to to do it myself as a learning experience before asking. I tried to do it earlier on my own but had compilation errors. I have limited time right now for hobbies so I was looking for a quick way to get going. If I do get it running I'll put it on my github account and post a link here.

  • ozpropdevozpropdev Posts: 2,792

    @blittled2
    Here's a example of a 64 pin I/O P1V build for the DE10.
    PortA is mapped to the GPIO Header and 4 of the 7 segment displays are mapped to PortB.
    Uses a propplug connected to the GPIO header (see the QSF pin assignment file).
    Use the Quartus programmer to load the top.sof file and then run the seven_seg_test.spin file to verify.
    Good luck!

    zip
    zip
    top.zip
    441K
    top.zip 440.8K
  • ozpropdevozpropdev Posts: 2,792

    Propplug connection pic.

    20220304_133638.jpg
    750 x 1000 - 302K
  • blittled2blittled2 Posts: 25

    Thanks ozpropdev! I'll give it a "spin" this weekend. :)

  • blittled2blittled2 Posts: 25

    I've been looking at the code ozpropdev graciously uploaded and I noticed that it was generated by a program titled P1V Toolbox. I did a search on it on the forum and GitHub and found only a text file describing how to set it up and the parameters you needed to set for different fpgas. Is this program proprietary? With the P1V being open source I would think it wouldn't be. If it is open source where would I find it?

  • ozpropdevozpropdev Posts: 2,792

    P1V_toolbox is not open source.
    Some very early executables were posted years back but as time progressed the complexity increased as IP was added.

    I hadn't used the tool for several years so it took me a while to get Quartus and the tool to cooperate successfully.
    If you have any questions about P1V I will try to answer them if my memory still works. :)

  • blittled2blittled2 Posts: 25

    Thanks for the info. Not having the top file being a verilog file confused me a little but I got it figured out. I want to use a softcore based on a microcontroller that I'm already familiar with to develop interfaces with it. I plan on creating some SPI IO expanders for the switches and 7 segment displays, a color map engine to take the 6 bit vga propeller driver to the 12 bit vga port and spi interfaces to the adc and accelerometer. Also redirecting the pinout to be like the Propeller A.S.C. If I feel real ambitious use Port B to interface to a driver that uses the SDRAM. That'll keep me busy for a long while :)

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