P1V on Spartan 7 FPGA (Arty S7 board)
Rayman
Posts: 14,755
Just got P1V working with a Diligent Arty S7-50 board with Spartan 7 FPGA.
Guess it's not a surprise it works since it was previously done with Spartan 6 board and that's where this version of the P1V code originated.
Just took the code that worked on ULX3S and Xyloni boards and changed clock source and constraints and it worked.
Thinking this is a good board to go forward with. It's available, affordable, and relatively barebones.
Also, this -50 version has enough LUTs to do a full P1, if needed.
Also nice is that DTR is connected to the FPGA as well as RX/TX, so don't need a Prop Plug. Also, there's a jumper on DTR that is handy to prevent USB reboots.
One thing I like about the Spartan 7 is that it has real TMDS output modes.
Was able to get HDMI output at 720p and 1080p relatively easily.
You can see here how I used the P2 Eval Digital Video Accessory to test that out:
http://www.rayslogic.com/Arty_S7/Arty_S7.htm
1080p is apparently outside of timing spec, but seems to work anyway.
One thing I'd like to do is get 720p or 1080p P1 style video output working.
Hoping I can eventually get that by using FPGA fabric instead of cogs.
No idea how to do that yet, but I'm learning.
Another nice thing about this board is the I/O on top is in an Arduino layout.
I'm pretty sure I'll find an Eagle layout that matches it somewhere.
I already have one that I put a P2 chip on once, but it doesn't have all the pins this one does.
Still thinking about the best way to store P1 code. Easiest might be to just add a real I2C eeprom chip to the setup. But, I think @Cluso99 figured a way to use the FPGA SPI boot flash chip for storing the P1 boot code. A more direct way looks to be just preloading the RAM with the code and changing the ROM from booter to rambooter. That's been done, but I haven't got it working yet...
Anyway, I'll post some Verilog once I get it cleaned up a bit.
Comments
Another Spartan 7 board I looked at was the Spartan Edge from SeeedStudio:
https://www.seeedstudio.com/Spartan-Edge-Accelerator-Board-p-4261.html
This one has HDMI port and is currently available at Mouser.
But, it has a smaller Spartan chip.
This one also has DTR connected to USB chip, but in a strange way that I'm not 100% sure will work.
However, Seeed does provide the Eagle layout for the board, which is a big deal for me, in case want to make my own FPGA board one day.
Just now I found there's already a P1V code for a different version of Arty:
https://forums.parallax.com/discussion/165514/p1v-for-digilent-arty-fpga-board-xilinx-artix-7/p1
Available here:
https://github.com/jacgoudsmit/P1V
Could be I should have started from that...
Think this is for the Arty A7 with Artix 7 FPGA. Haven't figured out all the differences between Artix and Spartan, but seems they are very similar but maybe Artix has a serdes that Spartan doesn't.
Maybe relatedly, I came across an actual P1V product:
https://www.xilinx.com/products/boards-and-kits/1-oz8bqb.html
Based on the Xilinx Zynq-7 FPGA.
I'm not 100% sure what's going on there though.
Looks like the design won a contest in 2015...
Noticed that the design is giving a timing error…. Guess I’m used to seeing that but having it work anyway.
@jac_goudsmit P1v version for the Artix version of Arty does not give a timing error. Tried starting from that but get timing error again.
Maybe I made a mistake getting Spartan version. Still it seems to work despite the timing error message…
~~Starting from @jac_goudsmit Pipistrello version (Spartan 6), finally got it to generate without timing errors.
Now, want to add some more "features" back in without breaking it.~~
Gives some warnings but critical timing error is gone now.
Source files below and project is here: http://www.rayslogic.com/Arty_S7/Arty_S7.htm
Deleting attachment because it fails vga_demo.spin
Uh oh, video doesn’t seem to be working right. Sync signal are all messed up.
Hmm. The previous version with failed timing gives good looking video signals. How strange...
I haven't worked on P1V for a long time, but I'm open for any pull requests once you fix the timing problems.
===Jac
@jac_goudsmit Thanks for all your work on the P1V repo, it's been a big help!
Found the problem with the Verilog, was a cut and paste issue. Was deriving cog clock signal from "clk" which is 100 MHz here instead of "clk_160", the IP derived clock source.
That looks to have totally messed up the vga driver. Surprising it worked at all.
Think I almost have it now.
Think it's finally in decent shape now.
This one has the "features" ala @SaucySoliton that turn off things like video, counters, and PortB.
The hub memory is based on @jac_goudsmit 's repo for Pipestrello where RAM and ROM are combined into one block and ROM is writeable, unscrambled, and loaded with as much of the original as you want.
Project files attached.