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Renesas Enters FPGA Market (at the CPLD end) — Parallax Forums

Renesas Enters FPGA Market (at the CPLD end)

https://www.edacafe.com/nbc/articles/1/1881841/Renesas-Enters-FPGA-Market-With-First-Ultra-Low-Power-Low-Cost-Family-Addressing-Low-Density-High-Volume-Applications

Info is sparse, but it covers what some others call CPLDs
The ForgeFPGA Family will serve applications that require less than 5,000 gates of logic, with initial device sizes of 1K and 2K Look Up Tables (LUTs).

still early release
ForgeFPGA engineering samples are available now, along with beta design software and a prototype development kit. The first ForgeFPGA device, the 1K LUT offering, is expected to be available in production quantities in Q2 2022.

No mention of supply voltages ?

This is coming from their SiLego originated division, which originally made OTP small package and low cost specific path SPLDs, with some simple analog.

A couple of their SiLego specific path SPLDs, reprogrammable versions, with wide Vcc

https://www.dialog-semiconductor.com/products/greenpak/dual-supply-greenpak/slg46824
https://www.dialog-semiconductor.com/products/greenpak/dual-supply-greenpak/slg46826

Mouser have those in stock in tqfn and tssop20 at ~ 50c/1k

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