Shop OBEX P1 Docs P2 Docs Learn Events
What happens to FIFO/Hub interface when in a debug ISR? — Parallax Forums

What happens to FIFO/Hub interface when in a debug ISR?

n_ermoshn_ermosh Posts: 294
in Propeller 2

What impact does the debug interrupt have on the system other than just being a high priority interrupt? Does it freeze hardware in its current state? There's a note in the docs that "by executing the ISR strictly in cog register space, this scheme does not interfere with the hub FIFO state, which would be impossible to reconstruct if disturbed by hub execution within the debug ISR." (page 53 of the original silicon docs). Doesn't the act of executing the debug ISR and loading the 16 instruction image from hub ram naturally mess up the FIFO state since it uses a fast block transfer?

And, what happens when the streamer or smart pins are active when a debug interrupt goes off? Do they continue executing, and therefore can't be paused like the main application?

Comments

  • Wuerfel_21Wuerfel_21 Posts: 5,053

    Block transfer doesn't mess up the FIFO. (Inversely, FIFO will steal memory cycles from a block transfer while it's active and in need of filling, but that is a timing disturbance only)

  • evanhevanh Posts: 15,915
    edited 2021-11-03 00:26

    A "fast block transfer" will be a dedicated state machine for each situation. SETQ+RDLONG has its own case for example. The FIFO's mechanism is also its own. Debug IRQ probably initiates, one after the other, both a SETQ+WRLONG and a SETQ+RDLONG (which is two independent state machines) to exchange some of cogRAM for hubRAM.

    Smartpins and local streamer will continue on their last op, but the cog won't be there for them if they need more input until the debug routine has completed.

  • n_ermoshn_ermosh Posts: 294

    So follow up question: How do you actually enter debugging? This is the process as I understand it, which wouldn't work, so I must be missing something:

    1. chip boots and runs cog 0
    2. during program execution, use hubset to enable debug interrupts
    3. use brk to trigger a debug interrupt for cog 0 (this is the part I'm confused about)
    4. run debug ISR

    From what I gather, brk only works if it was already enabled from within a debug ISR, so how do you get into a debug ISR to enabled using brk? Seems circular to me. Do you need to re-start the cog after hubset so that the coginit debug interrupt is triggered? Is there a way to enter the debug ISR without restarting the cog?

  • evanhevanh Posts: 15,915

    I've never coded such myself ... reading a little, it looks like the HUBSET precedes the target cog's COGINIT. The COGINIT generates a single IRQ in the freshly started cog where the BRK config can then be set. If wanting to enable debug for the currently running cog then you're in for restarting the running cog.

    Of course, the compilers have all this built in already.

Sign In or Register to comment.