P2 - some observations and questions

knivd

First, I am a big fan of the P2 concept!
In my view, this is what a 21st century MCU needs to look like - powerful but with universal simplicity in mind. The modern mainstream MCUs, despite being hugely powerful, are still implementing the same internal structure as in the 1970s. P2 does make a difference there.

There are a couple of things which made me wonder why done in the way the are, and I hope if someone from the design team at Parallax reads this, would be able to give some details:

1. The lack of internal flash. This is something puzzling, given that it is probably a no brainer from design perspective. Connecting an external flash is fine, but kills the single chip concept, and also increases the board room.

2. The dual 1.8/3.3V supply. Why not an internally generated 1.8V?

3. And this one is an actual problem - the power consumption. P2 draws current as much as a full blown Pi4 !! I suspect all those internal modules on each pin do take their toll. Is there any way to have them off by default and turn on only those who are actually needed for the application? Maybe even turn off the unused cores too? I can immediatly see at least ten application for which P2 would be a great fit, but with this consumption, none of them is viable. My hope is that P2.1 (or P3?) will be the same as P2, but with focus on efficiency - at least by an order of 10 times, so it can be a truly universal choice for development.

Wuerfel_21

@knivd said:
1. The lack of internal flash. This is something puzzling, given that it is probably a no brainer from design perspective. Connecting an external flash is fine, but kills the single chip concept, and also increases the board room.

The reason given for the lack of built-in flash (or any other non-volatile memory) is that the manufacturing process being used doesn't support it (and it would probably be expensive in terms of die area). I'd think that it'd be possible to create a variant with a flash die added in the same package, but the benefit of that would be dubious given all the other support circuitry that is needed.

evanh

@knivd said:
2. The dual 1.8/3.3V supply. Why not an internally generated 1.8V?

The potential max current draw is far too high for a linear regulator, the heat generated would need large die surface. And switch-mode of that power can't be done on die either, it would need complex packaging to accommodate the off-die inductor and caps.

3. And this one is an actual problem - the power consumption. P2 draws current as much as a full blown Pi4 !!

It depends massively on how the Prop2 gets used. Our testing of worst case is long way from normal use. It can run quite low power if you aren't pushing it. Also, remember that the design spec is 180 MHz, not the 300-360 MHz many of us are testing with.

Rayman

I seem to remember the design spec being 160 MHz. But, I do see 180 MHz mentioned here in the spec sheet:
https://www.parallax.com/propeller-2/documentation/#

The datasheet doesn't actually say. Actually seems to be an error there as in one place says VCO<200 MHz and another VCO<350 MHz.
That 200 MHz was probably the original spec, but in reality seems we got to 300+ MHz.

evanh

Probably still some Prop2-Hot hangovers.

Rayman

I think 160 MHz is the default in both FlexProp and Catalina due to this being the official target, way back when.

ManAtWork

@evanh said:
It depends massively on how the Prop2 gets used. Our testing of worst case is long way from normal use. It can run quite low power if you aren't pushing it. Also, remember that the design spec is 180 MHz, not the 300-360 MHz many of us are testing with.

BTW... I know that the worst case is around 2A @ 1.8V. But what is the lowest possible power consumption at 180MHz, for example, with only one cog in an idle loop and the other 7 shut down? The IO pins do not draw much power as long as they don't toggle at high frequencies and/or are loaded with DC current. I believe the biggest power sink is the hub ram interface with its many connections all over the chip.

Has anybody done tests about ways to minimize power consumption? For example, hubexec vs. cogexec, busy waiting vs. waitseX and so on?

AFAIK, the "no internal flash" decision and high power consumption of the P2 were all consequences of the limited budget for NRE costs. Parallax is a small fab-less company. A production process <90nm and with on-chip flash would have been way too expensive.

evanh

https://forums.parallax.com/discussion/comment/1482622/#Comment_1482622

Hubexec PGM4, 180 MHz, single cog: 242 mA.
Lots of waiting PGM1, 180 MHz, single cog: 205 mA
Lots of waiting PGM1, 180 MHz, all eight cogs: 168 mA (note it's lower than stopped cogs)

I did a newer run this year but that, I think, was only for eking out a little more on the max possible. I vaguely remember getting close to 2.5 Amps (calculated) based on current drawn from 5.2 Volt bench supply - which was a more reliable solution. The top end currents listed in that table are not entirely stable. I was having trouble with volt drop using an inline current meter on VDD rail. And thermals were an issue too, I had to keep using freezer packs to keep the PLL from slowing down.

ManAtWork

Thanks Evanh, that's interesting and explains why I don't get below 200mA with my encoder project although there are only 2 active cogs that do almost nothing. So waitx takes less power than busy looping and even less power than a stopped cog. Heavy hub RAM FIFO and streamer load takes the most power.