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adc smartpin x and y regs — Parallax Forums

adc smartpin x and y regs


I've been playing with P2 atod in FlexBasic.

pinstart(16, (p_adc_1x) or (p_adc) ,13 , 0)
  print int(rdpin(16)) 
  pausems 1000

This works and for an input of
0.0v I get 2980-2985
0.5v readings I get are 4592-4597 and
3.3v I get 13570 - 13579

from the scattered docs, I gather-
the value 13 above represents the regx= 001101
and that the two msbits '00' set up 'sinc2 sampling mode'
and that the bits '0-3' set up the number of sample bits= 2-18.

So 1101 sets the sample bits to what?
It looks like 14 bits as in 0-16384
If thats the case then 1110=14= 15bits?
and 1111=15= 16 bits?
so looks like bits value of bits 0-3 +1?

but if I substitute 14 for the above value 13 for regx I get a value of 0.

Can someone please explain and point me to some docs covering the adc x and y reg values and what sinc modes mean in real life.


ps had to put int around the print function as it was actually printing in hex (flexpin version 5.1- not the latest!)


  • tritoniumtritonium Posts: 477
    edited 2021-09-13 20:02

    waitup- just discovered

    pages 50 onwards..

    P2 hardware manual and it has nice tables so I will study before anyone goes to the trouble of formatting a reply..


  • JonnyMacJonnyMac Posts: 7,708

    I've attached my Spin2 code for a single-pin ADC -- it should be easy to port to FlexBasic. Remember that the ADC can read from below ground to above Vcc, so you need to calibrate the pin. For simple projects I only do this once. Some cases might want constant re-calibration (Chip demos that in PASM).

  • Hi Jon

    Thanks- as always very helpful. Interesting way of measuring 0v, 3v3 and scaling and calibrating and now I know what GIO and VIO are for!!!


  • evanhevanh Posts: 11,685

    X[3:0] reg setting specifies the sample period, in powers of 2, rather than the sample resolution. But the two are of course directly linked.

    So 13 is sample period of 8192 sysclock ticks. This happens to be the maximum supported in hardware. It requires at least 26-bit for each sync2 accumulator/register in the smartpin. They are known to be 27-bit. So what happens above a setting of 13 is the difference between two "decimations" can be larger than a 27-bit register can contain, making it an invalid sample.

  • evanhevanh Posts: 11,685

    A detail: It's sys-clock ticks for the built-in ADCs only. If using a smartpin to filter an external PDM bitstream from an external ADC, then X[3:0] specifies the period of external bit-clock ticks.

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