Alter D,S,R field of next instruction to (D + S) & $1FF. D += sign-extended S[17:9]. SYntax Question

Bob Drury

ALTR D,{#}S ALTD D,{#}S ALTS D,{#}S all have Alter D,S,R field of next instruction to (D + S) & $1FF. [17:9]. The indirection with BaseAddress (S) and Offset (D) makes sense but all seem
to refer to the fiirs bits of the register D,S,R [8:0] and the bits D,S,R[31:9] are all 0. I don't understand what D += sign-extended S[17:9] is trying to imply.
Regards
Bob (WRD)

evanh

It's an accumulate to the D register (index) using S[17:9] as the source addition data. Ie: The index can be stepped in large steps if desired.

I'd missed that that feature even existed for a long time.

In practice, I've found I end up with two S's. One for incrementing and one for not, because both actions are desired within the loop.

Bob Drury

evanh
ALTR Alter R Field result register address (normally D field) of next instruction to (D + S) & $1FF. D += sign-extended S[17:9].
ALTD Alter D field of next instruction to (D + S) & $1FF. D += sign-extended S[17:9].
ALTS Alter S field of next instruction to (D + S) & $1FF. D += sign-extended S[17:9].

Does this mean S= Offset S[17.9] + BaseAddressS[8:0]
D --> IndexD[8:0] + sign-Extended [17:9]
which results in either R,D,S being an "address" to alter the next instruction
address= BaseAdressS[8:0] + OffseD[8:0] + IndexD[8:0]
This would be good for stepping through a table with prescribed sections. I will try out.

Regards
Bob (WRD)

evanh

@"Bob Drury" said:
which results in either R,D,S being an "address" to alter the next instruction
address= BaseAdressS[8:0] + OffseD[8:0] + IndexD[8:0]

Sort of, as a post-accumulate. Ie: The offset appears at the next iteration.