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P2 Lexicon is Now Available as an Editable Google Doc — Parallax Forums

P2 Lexicon is Now Available as an Editable Google Doc

lozinskilozinski Posts: 70
edited 2021-07-06 04:29 in Propeller 2

This is a Lexicon for the P2 Parallax. You can read and edit this document on Google Docs. If there is a word you do not know, please ask on this discussion thread, and hopefully someone knowledgeable will describe the item and add it to the Lexicon. It would also be good to link from each word to the appropriate page.

Parallax P2 Lexicon

Thanks to: Christopher Lozinski, Jon McPhalen, @EvanH and anonymous..

This document describes some l of the terms used by the P2 Community.

ADS1256: A high resolution digital to anolog converter. 24-Bit, 30kSPS, 8-Ch Delta-Sigma ADC With PGA for Factory Automation and Process Control

Breadboard; a circuit board that you can easily insert capacitors, resistors and small IC’s into.

Breakout board: A breakout board exposes ("breaks-out") a circuit, function, or hardware module so it can be attached (usually temporarily) to a microprocessor. These are the "building blocks" used in early development to evaluate a design before a PCB is built.

Blinky Board: just an array of LEDs and current limiting resistors to visually show the status (on/off) of pins.

Buffered: In a hardware context, a device (gate, inverter, buffer) placed between an I/O pin and another device (often in the "outside world") to allow stiffer drive capability, waveshaping, or level conversion.

Chip: the guy who runs Parallax, and designed the chips and boards (?)

Cog: The P2 has 8 cpus each with their own memory, their own streamer, fifo, and LUTrAM and shared access to Hub resources.

Cordic: A system of math based on Logarithms. It allows for a smaller CPU than including a floating point unit.

DMA: Direct Memory Access.

DRAM: Synchronous DRAM (SDRAM) is the common form of memory used for main memory these days, Each DRAM cell is a single transistor that uses its gate capacitance to momentarily hold a charged voltage. Every cell of the array needs to be regularly (in milliseconds) read and rewritten to maintain that charge.

PSRAM: Pseudo DRAM. . PSRAM is not DRAM (SDRAM) based, it's just a marketing label slapped on DRAM with on-chip address generation and low pin count.

Dual Ported RAM. Random access memory which can be accessed simultaneously by two different circuits.

DuPont Cables:Common "jumper cables", a few inches in length, used to temporarily interconnect components/modules. "DuPont" was the company who originally made the socket/pin ends.

Edge Board. A very small board with the P2 installed. You can install the Edge board into a break out board.

EPROM: Erasable Programmable Read Only Memory: It has a window in the chip package exposing the die visually. This is used to shine UV light in and thereby erase the data, ready for programming again.

ESP8266. A very small, inexpensive circuit board with a CPU, some memory, and a wifi connection. You connect it to the P2 Eval board using the P2 Eval Adapter.

ESP32 A newer version of the ESP8266 with BlueTooth.

Evaluation Board. A circuit board with the P2 made by Parallax Inc.

Forth It is a stack based language, and requires very little space. Taqoz Forth is included in the Parallax P2.

FTDI Manufactures the USB chips used on many Parallax boards.

GPS Global Positioning system. Tells you where you are.

Header This is where you plug one circuit board into another one.

I2C. (Inter-Integrated Circuit) is a protocol that was developed by Philips. Used on the P1 for EEPROM memory.

IC Integrated circuit.

LFSR. Linear Feedback Shift Register. Used to generate an appearance of random numbers. The appearance is of an unchanging pre-shuffled order. Handy for procedural repetition.Random Numbers.

Loadp2: is used to load programs to the memory of a Parallax Propeller 2 ("P2") chip over a serial connection. It may also optionally execute programs from the P2 ROM (such as the built-in Forth interpreter TAQOZ) and/or send a scripted set of keystrokes to the application after loading.

LUTRAM There is Look Up Table RAM inside of each cog. This is a second block of SRAM in each of the eight Cog processors TThe reason for it being named that way is because the Streamers use it as a read-only table where it can provide colour palette register function and the like. . It is dual ported the same as the main "register" block but the ports have different use. One port is dedicated to the RDLUT/WRLUT load/store instructions of the Cog. The other port is primarily for the Cog's "Streamer" DMA engine but can also be shared with a dedicated neighbour Cog so that both see the same data in LUTRAM address space.

MQTT a Pub/Sub standard for IoT communications. Requires very low resources, and supports intermittent connections.

P2 the nickname for the newer Parallax chip.

Palette-ing was the traditional normal solution for displaying bitmapped images with computers when DRAM sizes were constrained to a few megabytes or even less. Not used much these days though. The colour range of the display was far greater than needed to be allotted to the image being displayed. So only the needed colours were loaded into a limited set of lookup registers inside the display controller chip and the bitmap was encoded to address those lookup registers rather than with the actual colours. This allowed reducing the bitmap size from 32 bits per pixel to 8 or less. Eg: The Amiga came out with 5 bits per pixel at a time when only 2 and 3 was the norm.

Parallax Inc, the company that makes the P2.

PCB Printed circuit board

Peter Jakacki The author of Tachyon and Taqoz forth

PROM: Programmable Read Only Memory. Also known as One-Time-Programmable (OTP).

PropLoader: is used to load programs into the memory of a P2 over Wifi. More here .

Prop Plug. A USB-to-3.3V_TTL_serial adapter -- made by Parallax for programming the P1 and the P2. If you try to program through a USb cable, every time it connects, it reboots the chip. Unless you use the Edge board with a connection that disconnects the Tx signal.

Pub/Sub Publications/Subscribe. Where some nodes on the network publish information, and others subscribe to it.

Pull Up Resistor Holds an IO pin at Vdd when that pin is floating (input state)

P2D2 a circuit board designed by Peter Jakacki

Raspberry Pi. A very low cost computer running linux.

PROM: Programable Read Only Memory.

Registers: These are the fastest type of memory. They are directly accessed by the cogs.

RS232: An EIA-specified hardware interface commonly used between "old school" computers and their terminals. Used today to communicate between microprocessors and remote devices over inexpensive cables. Generally slower than I2C and SPI, but capable of much greater distances.

SPI Serial Protocol Interface The P2 uses SPI flash for program storage.

Spin 2. The language developed by Parallax for programming the P2.

SRAM: Static Random Access Memory. It's the fastest of the RAM types. SRAM is heavily used in microcontrollers and also for cache RAM and certain buffers in faster CPUs. Each SRAM cell is a few transistors arranged as a simplified set-reset flip-flop.

Streamer is, combined with the FIFO, a DMA like engine for pacing data to and from the I/O pins. There's one in each Cog. There is a set of instructions in the Cogs for managing their respective Streamer.

Taqoz a Forth interpreter included in 2K of ROM. Peter Jakacki’s introduction.. Peter’s Dropbox. Using Taqoz Forth. Taqoz glossary

TX/RX Transmit/Receive -- these are generally used as pin names for those functions. Pin 63 is programming/debugging RX, Pin 62 is programming/debugging TX on the P2

UART: Universal Asynch Receiver/Transmitter. A hardware device that handles the framing and serialization of data to be transmitted, as well as the deserialization of data as it is received.

Comments

  • JonnyMacJonnyMac Posts: 7,649

    How many mistakes did I make?

    Quite a few -- you should consider doing a bit of research before publishing.

  • lozinskilozinski Posts: 70
    edited 2021-07-05 12:23

    I did make many mistakes in the original version, but within a day the document has become very useful. Overall I consider this a big success, a good contribution to this wonderfully helpful community.

    Welcome aboard!
    Chris

  • lozinskilozinski Posts: 70
    edited 2021-07-05 12:22

    Deleted.

  • There is no such thing as an ADS1526. You mean ADS1256. I’m also unhappy with your characterization of the rapsberry Pi as “not very reliable”. I’m using it in a professional context, and while there is something to be said about the general reliability of SD-cards (that affect it transitively), this is an questionable statement especially without any context. And within the context of this community comes IMHO off as hostile towards the Pi community.

  • evanhevanh Posts: 11,290

    The term LUT is not specific to FPGAs. LUT just means Look-Up-Table. The term is as old as the hills. It's use with respect to the Prop2 hardware is in reference to what's called LUTRAM inside each Cog. The reason for it being named that way is because the Streamers use it as a read-only table where it can provide colour palette register function and the likes.

  • Thank you for the great feedback. Here are the changed definitions. There are a few more terms we should define at the end.

    DMA: Direct Memory Access.
    Dual Ported RAM. Random access memory which can be accessed simultaneously by two different circuits.

    ADS1256: A high resolution digital to anolog converter. 24-Bit, 30kSPS, 8-Ch Delta-Sigma ADC With PGA for Factory Automation and Process Control

    LUTRAM There is Look Up Table RAM inside of each cog. This is a second block of SRAM in each of the eight Cog processors TThe reason for it being named that way is because the Streamers use it as a read-only table where it can provide colour palette register function and the like. . It is dual ported the same as the main "register" block but the ports have different use. One port is dedicated to the RDLUT/WRLUT load/store instructions of the Cog. The other port is primarily for the Cog's "Streamer" DMA engine but can also be shared with a dedicated neighbour Cog so that both see the same data in LUTRAM address space.

    Raspberry Pi. A very low cost computer running linux.

    What is Streamer?
    What is color palette registry?
    What is SRAM?

  • New Definitions:

    Loadp2: is used to load programs to the memory of a Parallax Propeller 2 ("P2") chip over a serial connection. It may also optionally execute programs from the P2 ROM (such as the built-in Forth interpreter TAQOZ) and/or send a scripted set of keystrokes to the application after loading.

    PropLoader: is used to load programs into the memory of a P2 over Wifi. More here .
    https://forums.parallax.com/discussion/173017/loadp2-update-for-p2-wireless-programming#latest

  • evanhevanh Posts: 11,290
    edited 2021-07-06 00:15

    SRAM: Static Random Access Memory. It's the fastest of the RAM types. SRAM is heavily used in microcontrollers and also for cache RAM and certain buffers in faster CPUs. Each SRAM cell is a few transistors arranged as a simplified set-reset flip-flop.

    The main other type used today is Dynamic RAM (DRAM) - Which further divides into Synchronous DRAM (SDRAM), which is the common form used for main memory these days, and Pseudo SRAM (PSRAM). PSRAM is not SRAM based, it's just marketing label slapped on DRAM with on-chip address generation and low pin count. Each DRAM cell is a single transistor that uses its gate capacitance to momentarily hold a charged voltage. Every cell of the array needs to be regularly (in milliseconds) read and rewritten to maintain that charge.

    And finally, there is the fastest memory of all - registers. These are built from flip-flops. Flip-flops are one of the basic building blocks in logic designs. Many data buffers are built from chains of registers. The register's speed is mainly due to being implicitly-addressed, it's the only option for the data flow, but physical placement inline in the circuit also helps.

  • evanhevanh Posts: 11,290
    edited 2021-07-06 00:40

    Streamer is, combined with the FIFO, a DMA like engine for pacing data to and from the I/O pins. There's one in each Cog. There is a set of instructions in the Cogs for managing their respective Streamer.

    Palette-ing was the traditional normal solution for displaying bitmapped images with computers when DRAM sizes were constrained to a few megabytes or even less. Not used much these days though. The colour range of the display was far greater than needed to be allotted to the image being displayed. So only the needed colours were loaded into a limited set of lookup registers inside the display controller chip and the bitmap was encoded to address those lookup registers rather than with the actual colours. This allowed reducing the bitmap size from 32 bits per pixel to 8 or less. Eg: The Amiga came out with 5 bits per pixel at a time when only 2 and 3 was the norm.

  • Here are the changes.
    Thanks for the work.

    Thanks to: Christopher Lozinski, Jon McPhalen, @EvanH and anonymous..

    SRAM: Static Random Access Memory. It's the fastest of the RAM types. SRAM is heavily used in microcontrollers and also for cache RAM and certain buffers in faster CPUs. Each SRAM cell is a few transistors arranged as a simplified set-reset flip-flop.

    DRAM: Synchronous DRAM (SDRAM) is the common form of memory used for main memory these days, Each DRAM cell is a single transistor that uses its gate capacitance to momentarily hold a charged voltage. Every cell of the array needs to be regularly (in milliseconds) read and rewritten to maintain that charge.

    PSRAM: Pseudo DRAM. . PSRAM is not DRAM (SDRAM) based, it's just a marketing label slapped on DRAM with on-chip address generation and low pin count.

    Registers: These are the fastest type of memory. They are directly accessed by the cogs.

    Cog: The P2 has 8 cpus each with their own memory, their own streamer, fifo, and LUTrAM and shared access to Hub resources.

    Palette-ing was the traditional normal solution for displaying bitmapped images with computers when DRAM sizes were constrained to a few megabytes or even less. Not used much these days though. The colour range of the display was far greater than needed to be allotted to the image being displayed. So only the needed colours were loaded into a limited set of lookup registers inside the display controller chip and the bitmap was encoded to address those lookup registers rather than with the actual colours. This allowed reducing the bitmap size from 32 bits per pixel to 8 or less. Eg: The Amiga came out with 5 bits per pixel at a time when only 2 and 3 was the norm.

    I think the most helpful part of the definitions was saying what exactly is in each cog. And what exactly is in the hub. it helps the reader get a high level mental model of the whole system. Up until now, I did not really understand streamers. I also need a section on paired cogs, and how they share memory.

  • evanhevanh Posts: 11,290
    edited 2021-07-06 05:32

    I've misled you a little with the description of the register ... processors don't access registers, they are built from registers (flip-flops) and logic gates. The difference between registers and block RAMs like SRAM is like the difference between a grain of sand and an area of beach, respectively.

  • evanhevanh Posts: 11,290
    edited 2021-07-06 05:36

    The difference between a register and flip-flop is only in the bit width of the register. If the bit width is just one then the register is a lone flip-fop.

  • evanhevanh Posts: 11,290
    edited 2021-07-06 06:17

    You've mistyped with "Pseudo DRAM". It's PSRAM, not PDRAM. But it is DRAM based. As in it is DRAM, the same as SDRAM, but with an on-die controller ...

  • evanhevanh Posts: 11,290

    Here's the Cog feature list from the main google doc:

    Each cog has:

    • Access to all I/O pins, plus four fast DAC output channels and four fast ADC input channels
    • 512 longs of dual-port register RAM for code and fast variables
    • 512 longs of dual-port lookup RAM for code, streamer lookup, and variables
    • Ability to execute code directly from register RAM, lookup RAM, and hub RAM
    • ~350 unique instructions for math, logic, timing, and control operations
    • 2-clock execution for all math and logic instructions, including 16 x 16 multiply
    • 6-clock custom-bytecode executor for interpreted languages
    • Ability to stream hub RAM and/or lookup RAM to DACs and pins or HDMI modulator
    • Ability to stream pins and/or ADCs to hub RAM
    • Live colorspace conversion using a 3 x 3 matrix with 8-bit signed/unsigned coefficients
    • Pixel blending instructions for 8:8:8:8 data
    • 16 unique event trackers that can be polled and waited upon
    • 3 prioritized interrupts that trigger on selectable events
    • Hidden debug interrupt for single-stepping, breakpoint, and polling
    • 8-level hardware stack for fastest subroutine calls/returns and push/pop operations
    • Carry and Zero flag
  • evanhevanh Posts: 11,290
    edited 2021-07-06 06:45

    The main benefit of DRAM, over SRAM, is cell size. Much more DRAM fits in the same die area.

    It's the same again with Flash. Although there the cell size is still a single transistor, like DRAM, but Flash trades speed for sensitivity and can encode multiple bits in the gate voltage. Flash, being an EEPROM tech, also doesn't have to keep refreshing the gate charge. The gate leakage is so low it'll hold for several years, or even decades for the lower densities, rather than milliseconds.

    The individual cells of Flash are relatively slow but back that with fixed incremental address ordering, large lines of amplifiers, and fast data buffers, you get acceptably fast burst transfer rates.

  • I am not sure why it is so hard to grok this chip. I have read that Cog features list many times. Each time it makes a little more sense. Compare it to the ESP32. CPU, wifi and BlueTooth. A very simple elevator pitch.

    A basic principal in human factors is that there should not be more than about 7 items in a list.

    Even that gorgeous image on these discussion boards does not do it justice. It sends a round robin message. Buyers think delay. I did. I went away and focusssed on the XMOS chip, until I realized it only sends 1 bit at a time messages between register sets on different tiles. It would be better if there were an image of a block of RAM being streamed to each cog simultaneously. A simple, true, if incomplete story. And instructions do indeed come in blocks.

    Then one could do an image zooming in on the hub. I still cannot list from memory what it connects to. I do not think that is my fault.

    Then there should be a focus on each cog Talking to pins, talking to a streamer. Talking to another cog. Talking to FIFO. Talking to Hub Ram Talking to 4 DACs and 4 ADC. Dual Port Register Ram, dual port look up ram. I sill do not know what the other port of the Register Ram talks to. My best guess would be FIFO. Again I do not think it is my fault that I cannot answer that question. I have certainly spent tons of time reading.

    The idea is to do a diagram of the hardware. Maybe not how it actually works, do not show all of the details, but conceptually, what a person needs to understand at the beginning level. Layer by layer, like an onion. ( What did Shrek say?? Ogres have layers like onions. ).

    Once a reader understands the hardware then add in what the hardware can do.
    Not in one massive list, in successive descriptions. An image of hardware connections. A list of software features. Some other lists as well.

    You've mistyped with "Pseudo DRAM". It's PSRAM, not PDRAM. But it is DRAM based. As in it is DRAM, the same as SDRAM, but with an on-die controller for generating addressing and bus width conversion too. Main purpose is to reduce pin count.

    For now I removed it. What exactly should it say.
    here is a wrong draft version.
    PSRAM: Pseudo RAM. . PSRAM is not DRAM based, it's just a marketing label slapped on DRAM with on-chip address generation and low pin count.

    As for the register definition, from an electrical engineers perspective you are correct. But from the software developers perspective, we think of registers as places where data comes and goes and is operated on. We think of the CPU as a black box made up of transistors. From a marketing perspective you really want to target newbies to IoT. Software developers. Not electrical engineers. Arduino users looking for an upgrade.

  • evanhevanh Posts: 11,290

    @lozinski said:
    As for the register definition, from an electrical engineers perspective you are correct. But from the software developers perspective, we think of registers as places where data comes and goes and is operated on.

    Ah, yes, addressable registers. Many for control configuration. Those are indeed a common use case. And the reason why they are registers at all is so that the control lines they decode to need to be static.

    Most registers are not memory map addressable. For example, all pipeline stages are groups of registers.

  • evanhevanh Posts: 11,290
    edited 2021-07-06 07:22

    @lozinski said:
    For now I removed it. What exactly should it say.

    Leave it out. It's hardly relevant. It was just another comparison initially. There is many more types of memories.

  • evanhevanh Posts: 11,290
    edited 2021-07-06 07:26

    @lozinski said:
    The idea is to do a diagram of the hardware. Maybe not how it actually works, do not show all of the details, but conceptually, what a person needs to understand at the beginning level. Layer by layer, like an onion. ( What did Shrek say?? Ogres have layers like onions. ).

    Parallax are working on documentation right now. Highly likely there will be a block overview included.

  • evanhevanh Posts: 11,290
    edited 2021-07-06 07:43

    @lozinski said:
    Then there should be a focus on each cog Talking to pins, talking to a streamer. Talking to another cog. Talking to FIFO. Talking to Hub Ram Talking to 4 DACs and 4 ADC. Dual Port Register Ram, dual port look up ram. I sill do not know what the other port of the Register Ram talks to. My best guess would be FIFO. Again I do not think it is my fault that I cannot answer that question. I have certainly spent tons of time reading.

    Both cogRAM ports are used in cog execution pipeline. The Props are unusual in that they are both designed around a block of SRAM for the "general register set" ... instead of actual registers! The Prop1 uses single ported SRAM, Prop2 is dual ported. There was an early prop2 design that used quad ported SRAM but got scrapped due to thermal concerns.

    Prop2 has a tick-tock like access cycle to cogRAM, with instruction fetch and ALU result writeback on the tick, and the two ALU operands fetched on the tock.

    EDIT: Also, instruction fetch can instead come from lutRAM or, via the FIFO, hubRAM. Hence why the instruction memory map overlays the cog/lut addresses on lower hub addresses.

  • msrobotsmsrobots Posts: 3,419

    I am more on @lozinski's side here.

    Using P1 for 10+ years now I barely remember my brain gymnastics to wrap myself around the different way of thinking you need to write a program for this controller. It is a shift almost as complicated as learning FORTH. Programming Propellers needs a different way to attack your problem but often results in very small, modular and understandable code.

    But you need to think different and starting from the view of one COG at the system and available resources might be more easy to understand for a beginner.

    And then explain how the COG's are sharing the attached components like CORDIC, shared HUB ram and Smart pins.

    Especially as there is a supposed family of P2's planned if it makes financial sense with different number of COG's, Pins and Memory.

    I think a main problem with understanding the Propellers is the invention of words Chip did to describe things, the whole HUB, COG thing was thought to be needed for understanding but is hindering a lot.

    All us old timers are used to it, most documentation is using it and someone new thinks - huh - what is that just to find out after hours of reading that a COG is a CORE, that a HUB is shared RAM and that the MIN instruction will give you the greater value and the MAX instruction the lesser one.

    @evanh and me followed the whole development process over a decade and are fascinated with details like dual ported RAM, code executable out of registers, LUT sharing, figuring out the timing delays of reads and writes of pins registered or unregistered, we (or at least me) are pushing things there, not for need but for fun.

    The beginner we need to catch should get the main message, not the details.

    Enjoy,

    Mike

  • evanhevanh Posts: 11,290

    Documentation is on the way.

    Labelling notable features is a good thing. It helps get away for constantly using long descriptions, or worse, leaving people confused about context when over-using more common labels. The lexicon can contain those long descriptions, and even examples I guess.

  • New additions to the lexicon

    PNut: Factory supported development tool Chip adds features and tests the compiler with his stripped-down PNut for Windows. Once these features are proven to work, Jeff moves them into the official Propeller Tool for Windows.

    Goertzel Algorithm. Calculates the size of a particular frequency component of a time based signal.

    It would be good to add in the names of all of the important software packages.

  • lozinskilozinski Posts: 70
    edited 2021-07-17 09:17

    New additions to the Lexicon:
    really to what interests me.

    Spin2CPP: is a program for converting Spin, BASIC, or C code to binary, PASM (Parallax Propeller 1 assembly), P2ASM (Parallax P2 assembly), C, or C++.

    FlexSpin: is a compiler for Spin (and much of Spin2), BASIC, and C which can produce binaries for P1 and P2. FlexProp is a very simple IDE which uses flexspin.

    FlexProp: is a simple IDE for programming the Parallax Propeller2 and/or Propeller1. It is a front end for the flexspin compiler, which can compile Spin, BASIC, PASM, or C code to Propeller 1 or 2 assembly language.

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