What should my VCO divider setting be?
I'm having trouble understanding what is meant by "VCO" in the P1 manual.
I've been following the information on Page 97, where it states:
For stable operation, it is recommended that the VCO frequency be kept within 64 MHz to 128 MHz. This translates to an NCO frequency of 4 MHz to 8 MHz.
I'm running from an external 5 MHz xtal, and using PLL1X for testing purposes (because my logic analyser is not fast enough at full PLL16X).
Does this mean that the VCO is not stable if I'm using PLL1X @ 5 MHz?
I want to use CTRB in mode %01000 (POS detector) and I want it to sample the APin every 4 clock cycles precisely (in other words, I want to be able to synchronise the sampling with the execution of several sequential instructions. That means I want the counter to sample at a rate of 1.25 MHz.
What should my PLL divider be set to in this case?
I think I've tried everything and nothing seems to give me the results I want.