What should my VCO divider setting be?

Cabbage

I'm having trouble understanding what is meant by "VCO" in the P1 manual.

I've been following the information on Page 97, where it states:

For stable operation, it is recommended that the VCO frequency be kept within 64 MHz to 128 MHz. This translates to an NCO frequency of 4 MHz to 8 MHz.

I'm running from an external 5 MHz xtal, and using PLL1X for testing purposes (because my logic analyser is not fast enough at full PLL16X).

Does this mean that the VCO is not stable if I'm using PLL1X @ 5 MHz?

I want to use CTRB in mode %01000 (POS detector) and I want it to sample the APin every 4 clock cycles precisely (in other words, I want to be able to synchronise the sampling with the execution of several sequential instructions. That means I want the counter to sample at a rate of 1.25 MHz.

What should my PLL divider be set to in this case?

I think I've tried everything and nothing seems to give me the results I want.

Wuerfel_21

The VCO and its divider are only relevant for the counter's PLL modes.

jmg

@Cabbage said:
I want to use CTRB in mode %01000 (POS detector) and I want it to sample the APin every 4 clock cycles precisely (in other words, I want to be able to synchronise the sampling with the execution of several sequential instructions. That means I want the counter to sample at a rate of 1.25 MHz.

I think that detail is not supported by a single P1 counter.

In POS detector the pin is an adder-enable, so every sysclk it will check that pin, and if hi, adds. A high pin will add 4 times, over the 4 clock cycles.

I see the counter does have two-pin LOGIC modes, so you might be able to kludge what you want with another pin and the second CTR block

If the sample pin is driven from a DUTY out configured counter, you get spaced 1 clock pulses. for your 4 clocks, set so this overflows once every 4 adds.
your pin-sampling adder then uses MODE LOGIC A & B so it adds once only provided both pins are high. If your test pin is low, no add occurs.
An advantage here is you can scope the sample-enable pin to verify timing.

I'm not sure what happens if you modify FRQA on the same sysclk that PHSX is trying to add it , but the other 3 sysclks are likely safe.
Worst case could be some mix of new/old bits of FRQA apply. It should be possible to test for that.

Addit: ISTR there are some fish-hooks around relative pin delays, so not all pins are quite created equal. The P1 has an OR tree that combines the COGs pin signals.
I find this, which hints at pin specific caveats
https://forums.parallax.com/discussion/comment/947662/#Comment_947662
and ISTR also mention of the 1 cysclk narrow DUTY pulse, being missed on some combinations. With a 1 clock wide pulse, that can occur if tplh is slower than tphl, narrowing the pulse.

Addit 2: Search gives no sign of pin differences yet, but I did find a code example using exactly the approach above, of two CTRs and a (spare) pin and gated MODE LOGIC A & B
https://forums.parallax.com/discussion/comment/1466234/#Comment_1466234