Data Sheet Pin DIR/OUT Control (%TT) Table

Bob Drury

The "Pin DIR/OUT Control (%TT) Table" has the following statements:

'DAC_MODE' is enabled when P[12:10] = %101
'BIT_DAC' outputs {2{P[7:4]}} for 'high' or {2{P[3:0]}} for 'low' in DAC_MODE

I am confused what P[12:10] stands for does this mean Pins P10 P11 P12 are dedicated to "DAC_MODE"
should the above be P[12:10] = M[12:10] and P[7:4] = M[7:4] and P[3:0] = M[3:0]
Is there something I need to read to understand this table?

Thanks
Bob (WRD)

evanh

No, Chip used M[12:0] in the low-level pad-ring pin mode table. But these are set with the WRPIN instruction so that conflicts with the %MMMMM smartpin modes in the same instruction, so he named them the P bits for WRPIN.

And just to add a little more confusion, he's used B[12:0] for the newest diagrams of the low-level pin modes. The reason there is that P[12:0] conflicts with pin naming as you've just found out.

I've suggested he use C[12:0] in the future and I think he agrees with that choice. But it takes time to go through all the docs and change the naming.

evanh

Only a couple of weeks back - https://forums.parallax.com/discussion/comment/1523886/#Comment_1523886
Though the issue had been raised years back in a different manner - someone was wanting the sheet with M field changed name to P field to match the WRPIN docs.

Bob Drury

EVANH thanks for your response.
Is there actually a "Pad Mode" set of bits and a "Smart Mode" set of bits? The "Pad Mode" bits have 4 bits xxxx_CIOHHHLLL and the "Smart Mode" schematics
have 5 bits xxxxx_MMMMMMMM . If so how are the "Pad Mode" and "Smart Mode" bits related? Does WRPIN command do something to relate these?
Is there something I should read to clear up this confusion. Again thanks for your help.
Regards
Bob (WRD)

evanh

Yes, two parts. And yes, does need to be better defined in the docs. Here's a block diagram of what is associated with each I/O pin:
https://forums.parallax.com/discussion/171420/smartpin-diagram-now-with-p-p-bit-mode-table

You can see the "smartpin" is one block of many. Albeit a large block in terms of percentage silicon for each pin.

PS: There is indications in each block as to which fields of WRPIN apply.

Bob Drury

Thanks EVANH. I was obviously going the wrong way In trying to follow tables.
Regards
Bob (WRD)

evanh

There is little hidden details. One that I facepalmed on just recently is, when in %101 DAC_MODE, the bottom 8 bits of those 13 bits becomes the DAC databus. It's an obvious statement when looking at the DAC mode list ... but when looking for extra ways to configure all the parts, you can find yourself trying to turn on parts that become inaccessible because those config bits vanish when in DAC_MODE.