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130nm shuttles for free — Parallax Forums

130nm shuttles for free

RamonRamon Posts: 477
edited 2021-06-09 15:03 in Propeller 2

@"Ken Gracey" @cgracey

There are currently two options of some kind of "free" mpw shuttle on 130nm:

https://efabless.com/open_shuttle_program/2
https://efabless.com/chipignite/2106Q

The first shuttle option is entirely paid by google but requires the project to be open sourced in git (P1 already is there).

The second shuttle option actually requires some money, but seems a good option to experiment in 130nm. (and maybe allows commercial projects)

Within this second option, there are "Two pricing options:
$9,750 for 100 QFN or 300 WCSP parts
or 1000 parts for $20 each"

Submissions (tape out) closes next week (June 18) for both options.

Comments

  • Definitely, Chip could seize the opportunity. However, the con I see is that Google may want to take over the design. So, probably this could be used to test useless bits and pieces that would only work together with something. Eg. separate DACs, ADCs, some core.

    Mind that Google is developing their own silicon and is probably in need of ideas.

  • hinvhinv Posts: 1,058

    What node is the current P2 done in?

  • Cluso99Cluso99 Posts: 17,772
    edited 2021-06-09 23:42

    180nm
    OnSemi ONC18 IIRC

    But don't forget the I/O is Parallax custom (basically hand laid and converted).

  • msrobotsmsrobots Posts: 3,365

    90 would be the next step, but first we need to buy 10,000,000 P2s...

    Mike

  • @msrobots said:
    90 would be the next step, but first we need to buy 10,000,000 P2s...

    Mike

    There is always someone to help with that. About the 130nm process, I think it would be enough to solve the current die size related limitations and the project could go with more cores (even, perhaps, 16). However, I would suggest cutting Google as the middleman, as Google itself is fabless, so there would be no real gain.

    90nm is too expensive and too bleeding edge. As for 130nm, Infineon is providing it: https://www.infineon.com/dgdl/C11N-br-2007-Blue%5B1%5D.pdf?fileId=db3a304317a748360117b0c6ec4f6809 . However, I don't know if it is good for a future Propeller, since I know nothing about microelectronics.

  • AJLAJL Posts: 384

    A nearly 20 year old fab process is bleeding edge?!?!

  • samuellsamuell Posts: 554
    edited 2021-06-10 03:21

    I said "too bleeding edge" instead of just "bleeding edge". There is a difference. 90nm is still not available for cheap, for a reason. It could be 50 years old, as far as I'm concerned. My point is: it is not an "easy" process to fab with, and there are not many fabs that can do 90nm.

    If you think about it, it is the same with C compiler standards. I still use C99 because it is proven. Just an example.

  • AJLAJL Posts: 384

    Then I’d suggest ‘expensive’ would be a better term to convey your meaning.

    Bleeding edge conveys a sense of immaturity that 90 nm doesn’t have.

  • Beau SchwabeBeau Schwabe Posts: 6,466
    edited 2021-06-11 14:10

    Considering the technology is down into the single digits now 6nm, the unit the layout tools uses is now referenced in Angstroms. 6nm = 60 Angstroms .... so 130nm is absolutely huge by today's standards.

    It boggles my mind to think that a stable Aluminum molecule consisting of 2 Aluminum atoms is about 3 Angstroms wide. With 6nm technology, that's only a 20 molecule wide conductor.

    When I worked at National Semiconductor, I was characterizing standard cell structures for 65nm and 45nm ... that was toward the end of 2004

  • Cluso99Cluso99 Posts: 17,772

    @"Beau Schwabe"
    Yes, boggles the mind!

    There has to be a fundamental limit and we seem to be approaching that fast now.

    Of course stacking layers will get us a continued increase in the number of transistors that can be placed in a physical space.

    I still want someone to work out how we can easily make (at home) a rudimentary IC like a single gate. I know a few have done it but as yet it's not ready for the masses. Something along the lines equivalent to like we now have cheap 3D printers.

  • evanhevanh Posts: 11,064
    edited 2021-06-12 02:10

    @Cluso99 said:
    I still want someone to work out how we can easily make (at home) a rudimentary IC like a single gate. I know a few have done it but as yet it's not ready for the masses. Something along the lines equivalent to like we now have cheap 3D printers.

    For education or commercial? A single gate isn't of much commercial value.

    PS: Someone posted a youtube link on these forums of a person doing all the lithographic steps by hand. It was just one gate I believe. Great for education.

  • This guy is doing massless photolithography in his garage. Definitely not for the masses though...

    https://youtube.com/c/SamZeloof

  • Cluso99Cluso99 Posts: 17,772

    I’ve seen some make gates but the equipment is prohibitive. I’m looking for something that can be done on a small budget sub $500 and a decent chance of success. If a single gate can be made, the we are off to a start to make some simple logic ICs.

  • evanhevanh Posts: 11,064
    edited 2021-06-12 10:37

    I guess micron grade features would be doable with simple mechanical plotting arrangement. Eliminate the whole lithography approach and use CNC additive construction instead.

    Wouldn't be using silicon, it would be materials that can be liquefied at say 300 C. Conductors and insulators should be easy but a transistor in semiconductor might be the hardest part. I have no idea if they can be made without doping.

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