Providing clock from one P2 to multiple others.

msrobots

I would like to provide the clock input for one P2 from another P2's smart pin.

Can I (common ground and power) connect the pins directly and what distance is reasonable while providing say 20 Mhz.

curious,

Mike

Rayman

I'd think that would work over feet as long as you have a ground plane under the clock trace and keep other signals somewhat away.
Maybe I'd put a termination resistor near the clock input of the other P2.

You could pick the 2.0 V, 75 Ohm driving mode and try to make the trace impedance 75 Ohm and then match with a 75 Ohm termination resistor.
But, it may be better to just make it the regular, 3.3 V fast drive.

If it really was feet, you could use a shielded cable, maybe a thin coax cable...

jmg

@msrobots said:
Can I (common ground and power) connect the pins directly and what distance is reasonable while providing say 20 Mhz.

What distance do you have in mind ?
Between boards, you may consider differential signaling to reduce RFI.

msrobots

Well a feet would be overkill, I am thinking about a couple of inches for the project.

My basic thinking is, if provided with the same clock source the connected P2's would run more in sync for fast inter P2 transfers.

Not sure if that is even valid

Mike

dMajo

I think that for the max sync and lowest jitter the best it should be to take the clock from the P2 crystal connection pins (the out pin, X2) and if you have multiple 'slave' P2 feed them after a non-inverting gate driver to avoid loading the main P2 oscillator. You also save a pin.

msrobots

But after PLL and mul/div how accurate would a say 320Mhz clock be, comparing two sub-nodes?

Mike

evanh

The way to do it is use an external 20 MHz oscillator chip evenly fed to XI on all prop2's. XO left unconnected. Then setup the PLL in each prop2 with the same mode. The only difference in usual HUBSET mode number is %CC becomes %01 instead of %10.

dMajo

Evanh's option is still better, but requires an external oscillator, which may still require external gate drivers to drive multiple P2s, depending on the oscillator's drive capability and number of P2s.
Regarding the accuracy of the so derived multiple 320M clocks I think that only @cgracey can answer on the P2's PLL jitter and stability characteristics

Rayman

Feeding all the P2s with the same, say, 300 MHz source would be the best option, right? Can one do that?

jmg

@msrobots said:
But after PLL and mul/div how accurate would a say 320Mhz clock be, comparing two sub-nodes?

An external CMOS clock would be best, feeding all P2s - then they all have identical CLKIN conditions.
There will be some phase jitter across units, I'm not sure if anyone has nailed down jitter-ps values, but it is known that higher PFD values have least jitter.

@Rayman said:
Feeding all the P2s with the same, say, 300 MHz source would be the best option, right? Can one do that?

It's not easy to route 320MHz to multiple nodes on a board, and Clock generators usually top-out at 200-250MHz region for CMOS, using LVDS for values above that.