P2 Frequency / Temperature Logging
VonSzarvas
Posts: 3,450
Hi everyone !
Here's some initial data of temperature rise of the P2 Edge module whilst being run at various frequencies and current loads. (Data collection is in-progress, and I'll update the spreadsheet with more variants soon!))
https://docs.google.com/spreadsheets/d/1diJEpmfaivDfvua6Xn7UwfrTO1AYVBwkP2GloVyOAbs
Photos of the setup and the code being used : https://drive.google.com/drive/folders/1aC1diOju06bQN6bOJ_SOmivMhPc1xtKr
Briefly though...
- Temperature controlled oven with P2 Edge as the DUT.
- Eight thermocouples (3 each side of the Edge module, 1 inside oven temp, 1 outside oven temp),
- Inline high side current monitoring of the 5V supply, between the bench supply and DUT
- Vout monitoring of VIO24
- Two frequency logs (clkfreq/100 and DAC toggle on pin 48 for some tests- else it will show as zero)
Edit: Test code file attached (power_check4.spin2)
Comments
Nice start. It'd be good to capture RCslow and RCfast at different temperatures too, if possible. My recollection is that RCslow varied a fair bit, but RCfast was stable across temperatures.
That one is impressive partly because the voltage regulator stood up. But the Prop2 performance might just be too good. Are you monitoring a toggle frequency to know the PLL frequency is maintained?
And what temperatures is the Edge Board reaching? Is there a probe with good thermal contact to the ground plane/exposed pad?
Yes, thermocouple #6 is right in the middle of the P2, on the back.
Thermocouples (Degrees C) #1 #2 #3 #4 #5 #6 #7 #8
1. Switcher inductor
2. P2 chip top (top-left)
3. P2 chip top (bottom-right)
4. Oven ambient
5. pcb back - P2 Edge logo
6. pcb back of P2 chip
7. pcb back of switcher
8. room temp
The frequency log is column S, captured from an output on pin 57
OHHHH! Lol, I was only looking at the Index page ....
Gazeepers! Lot's more fun beyond the index !!
Okay, something about the test isn't working right. Here's test 28 where the measurements transition from 775 mA to lower 68 mA current. Some sort of lockup occuring I presume.
116C heatsink temperature isn't near high enough for that power level. The 300 MHz tests are 20C higher, at 130C, for the same 700-800 mA and even the 300 MHz tests are suspect, imho.
I have real doubt of the validity of the frequency readings. I don't believe 300 MHz is possible above 100C let alone 320 MHz.
that's test 27, which failed.
Oops, yep, 27. I was looking at 28 at same time. And I'll start eats me words on the temperature curve too. Just doing the testing myself now (Which I could have done years ago!) and the PLL allows over 340 MHz at 100 °C die temperature. Way higher frequency than I expected.
And the PLL slope is something around -0.75 MHz/°C. Although it's not exactly linear.
EDIT: It's looking like the PLL self-limiting is proving not to be 100% protective though. That'll be why you're getting crashes.
EDIT2: Here's my measured points for die temperature vs PLL settling frequency:
MHz degC ======================== 330 122 340 106 350 92 360 78 370 65 380 53 390 41So, if one was to ensure a die temperature of 25 °C then 400 MHz should be possible. Although lower would be advised so as to stay away from the crash prone range. And of course if doing a lot pf processing then a lot more leeway is needed for the temperature gradient between cooling and junction.
On a sample size of ???
It's all rough numbers Cluso. If you want to be cautious then you'd never even get close to those numbers.
Also to share that my tests are sample size of 1 whilst we figure out the sweet spots and trends.
After that we can reduce the number of tests to some specific settings (perhaps 2 or 3 variants) and repeat them across multiple devices.
Von,
Have you got any idea on calculating, in say test #29, what the temperature difference might be between the ground plane on the back of the Edge to the die junction temperature?
Whole board power is 3 Watts. You've got 124 °C for the ground plane. I guesstimate the PLL starts limiting the 320 MHz at around 138 °C, maybe 140. So junction temperature must be below that. And to not have crashes needs some buffer range below too.
TJa for the P2 package is 18.2 C/W
One thing we don't know is the real power into the P2 chip- The LDOs won't be taking much of the share but I figure we could get closer to reality by removing that switcher (and feeding in a monitored 1.8V to the P2). And we also ensure the switcher is not hitting a thermal limit and shutting the P2 down.
I'm modding an Edge now and will start baking shortly!
Hmm, that's too large. That'll be without any heat sink attached. The more useful figure would be junction to exposed pad.
The Eval Board has a removable jumper just for that.
Yeah, that's the package only. It's based on being mounted on a certain amount of copper which the Edge just about matches, so that reason (and for consistency at this point) is why the Edge is next in the oven!
EVAL should run cooler to some extent (or at least the curve will be less steep). Eventually in a closed box everything just gets toasty!
I've updated the first post with a link to some photos of the test setup. A pair of digital heat guns controlled by P2 Edge / JonnyMac combo. The oven is just a convenient heat insulated box (ahem, to some degree). The oven is unplugged and relies on the heat guns heating function.
The tray with all the articulated arms allows us to set up the DUT outside the oven. All the thermocouples are "rammed" into the DUT with a dolop of https://www.qoltec.com/product/qoltec-thermal-grease-515-wm-k-1g-grey
(Thermal conductivity : 5.15W/mK, Thermal resistance : max. 0.004°C/W)
Thanks, I'll check back in after work. I'm way late for bed now.
Hi VonSzarvas
Out of curiosity; can you tell what's the kind of 20.000 MHz crystal (or clock oscillator) (mfg, type, etc) is assembled at the P2-EDGE(s) you are using during the tests?
Are there any specific temperature probe "tacked" to its (their) package(s)?
BOM for Edge revA says: Epson TSX-3225 20.0000MF20G-AC3
Thanks evanh!
I was aware of the BOM, but was having some difficulty in finding the exact model.
Epson Europe just gave a helping hand, and now I have some links, but still not sure of the matching part, because there's more than one (BOM's spec'd CL of 9 pF did helped in restricting the search. Now I have just four, differing mainly in Temperature Range Frequency Stability over Temperature, just the data I was looking for).
Here are the ones I found:
Turns out I had done this years ago in fact. But it was only for the revA silicon. And it produced an interesting outcome too:
That testing was bit-bashing a pin for measuring the frequency. If I'd used a smartpin it may have faired better with /1 mode.
The interesting part is there is notable shift in the measured temperatures vs frequencies as the XDIVP divider is increased.
Ha, and idling all the cogs, instead of leaving them stopped, has an improved impact too.
rep #1, #0 waitx #500EDIT: Here's my up-to-date source.
con XTALFREQ = 20_000_000 'PLL stage 0: crystal frequency XDIV = 2 'PLL stage 1: crystal divider (1..64) XMUL = 45 'PLL stage 2: crystal / div * mul (1..1024) XDIVP = 20 'PLL stage 3: crystal / div * mul / divp (1,2,4,6..30) TPIN = 9 dat org 'put other cogs into a sleepy state hubset #$f0 'safe RCFAST mov pa, #7 .loop coginit pa, #@pause djnz pa, #.loop waitx ##1000 'wait for other cogs to bed down 'Set frequency ( sysclock/1000 ) output at smartpin TPIN dirl #TPIN wrpin #SPM_NCO_FREQ, #TPIN wxpin FRQperiod, #TPIN wypin FRQphase, #TPIN dirh #TPIN 'Use accurate crystal oscillator and PLL instead of RCFAST hubset ##CLK_MODE 'power up external 20 MHz crystal and PLL waitx ##25_000_000/100 '10 ms pause for stablising hubset ##CLK_MODE | XSEL 'switch over to PLL as system clock source 'Twiddle thumbs while smartpin does job .pause rep #1, #0 waitx #500 jmp #\.pause jmp #\.pause jmp #\.pause jmp #\.pause '-------------------------------------------------------------- FRQphase long $8000_0000 '32-bit fraction of oscillation FRQperiod long 500 / XDIVP 'sysclocks per fraction ( sysclock/1000 ) '-------------------------------------------------------------- org 'Twiddle thumbs while smartpin does job pause rep #1, #0 waitx #500 jmp #\pause jmp #\pause jmp #\pause jmp #\pause con ' Clock modes: %0000_000e_dddddd_mmmmmmmmmm_pppp_cc_ss XOSC = %10 ' OSC ' %00=OFF, %01=OSC, %10=15pF, %11=30pF XSEL = %11 ' XI+PLL ' %00=rcfast(20+MHz), %01=rcslow(~20KHz), %10=XI(5ms), %11=XI+PLL(10ms) XPPPP = ((XDIVP>>1) + 15) & $F ' 1->15, 2->0, 4->1, 6->2...30->14 CLOCKFREQ = round(float(XTALFREQ) / float(XDIV) * float(XMUL) / float(XDIVP)) CLK_MODE = 1<<24 | (XDIV-1)<<18 | (XMUL-1)<<8 | XPPPP<<4 | XOSC<<2 SP_OUT = (%1 << 6) ' enable digital output when DIR operates smartpin SPM_NCO_FREQ = %00110_0 |SP_OUT ' NCO frequency, X[15:0] = base period, Z += Y, OUT = Z[31] SPM_PULSES = %00100_0 |SP_OUT |(1<<7) ' pulse/cycle output, X[31:16] = base period, X[15:0] = duty of period