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STREAMER - I beg you example !

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  • evanhevanh Posts: 10,954
    edited 2021-04-02 01:37

    Oh, bugger, the "a" bit doesn't work that way either! I think I got it right now:

    eg:  Shifting out %1000_1100_1110_1111_0111_0011_0001_0000 in 4-bit elements:
    
      Step | D3  D2  D1  D0       ( "a" mode bit set, some messed up big-endian in a little endian system )
    -------+-----------------     ( Streamer mode:  %0110 dddd eppp p101 )
        1  |  0   0   0   1
        2  |  0   0   0   0
        3  |  0   1   1   1
        4  |  0   0   1   1
        5  |  1   1   1   0
        6  |  1   1   1   1
        7  |  1   0   0   0
        8  |  1   1   0   0
    
      Step | D3  D2  D1  D0       ( "a" mode bit clear, little-endian )
    -------+-----------------     ( Streamer mode:  %0110 dddd eppp p100 )
        1  |  0   0   0   0
        2  |  0   0   0   1
        3  |  0   0   1   1
        4  |  0   1   1   1
        5  |  1   1   1   1
        6  |  1   1   1   0
        7  |  1   1   0   0
        8  |  1   0   0   0
    
  • RamonRamon Posts: 476

    I am testing the three 4-bit modes and I am not able to see any difference between them:

    0110 dddd eppp p00a <long> imm 8 x 4 -> 4-pin + 4-DAC1 4 out %dddddddd_cccccccc_bbbbbbbb_aaaaaaaa
    0110 dddd eppp p01a <long> imm 8 x 4 -> 4-pin + 2-DAC2 4 out %00000000_00000000_dcdcdcdc_babababa
    0110 dddd eppp p10a <long> imm 8 x 4 -> 4-pin + 1-DAC4 4 out %00000000_00000000_00000000_dcbadcba
    

    This is the test code. What am I doing wrong ??

    CON
      _clkfreq = 4_000_000
      DOWNLOAD_BAUD = 115_200
      rx_pin   = 63
      tx_pin   = 62
      baud     = 115_200
    
      OUTPIN   = 36     ' Using Pins 36 to 39 (D0..D3)
    
    OBJ
      ser: "spin/SmartSerial"
    
    PUB main() | md, i
    
      ser.start(rx_pin, tx_pin, 0, baud)
      waitms(4000)
      org
            setxfrq ##536                       'streamer freq: 1 Hz
      end  
      org                      
            drvl    #OUTPIN                      'pin 36 D0 = output, low
            drvl    #OUTPIN +1                   'pin 37 D1 = output, low
            drvl    #OUTPIN +2                   'pin 38 D2 = output, low
            drvl    #OUTPIN +3                   'pin 39 D3 = output, low
      end
      waitms(40)
    
      md := %0110_0000_1100_1000<<16 + $FFFF  'streamer mode: imm 8x4, 4-pin, %dddddddd_cccccccc_bbbbbbbb_aaaaaaaa
      ser.printf("md : %x\n", md)
      org
            xinit   md, ##%1100_1100_1100_1100_1100_1100_1100_1100  ' 
            'xinit   md, ##%1111_0000_1111_0000_1111_0000_1111_0000  ' 
      end
      waitms(10000)
    
      md := %0110_0000_1100_1010<<16 + $FFFF  'streamer mode: imm 8x4, 4-pin, %00000000_00000000_dcdcdcdc_babababa
      ser.printf("md : %x\n", md)
      org
            xinit   md, ##%1100_1100_1100_1100_1100_1100_1100_1100  ' 
            'xinit   md, ##%1111_0000_1111_0000_1111_0000_1111_0000  ' 
      end
      waitms(10000)
    
      md := %0110_0000_1100_1100<<16 + $FFFF  'streamer mode: imm 8x4, 4-pin, %00000000_00000000_00000000_dcbadcba
    
      ser.printf("md : %x\n", md)
      org
            xinit   md, ##%1100_1100_1100_1100_1100_1100_1100_1100  ' 
            'xinit   md, ##%1111_0000_1111_0000_1111_0000_1111_0000  ' 
      end
      waitms(10000)
    
      repeat
        org
            nop
        end
    

  • evanhevanh Posts: 10,954

    The only difference in those modes is the data patterns to the four DAC channels. Which needs the DACs enabled. For logic output, they're all the same mode.

  • RamonRamon Posts: 476

    Oh, Thank you!

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