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RPi Pico - Do Creators/Users/Reviewers know about the Propeller 2? — Parallax Forums

RPi Pico - Do Creators/Users/Reviewers know about the Propeller 2?

Jeff MartinJeff Martin Posts: 760
in Propeller 2

RPi Pico has a patent-pending programmable I/O controller. Not sure how closely it resembles our Smart Pins.

https://www.allaboutcircuits.com/news/desginers-take-raspberry-pi-first-microcontroller/

Comments

  • Jeff MartinJeff Martin Posts: 760
    edited 2021-03-19 02:21

    When I showed this to Chip, he said:

    So, two ARM cores and eight PIO's. Patented, too. I was looking at the instruction set for the PIO. I think it only holds 31 instructions. It's basically for timing output and input.

  • Christof Eb.Christof Eb. Posts: 1,213

    Well, no, they or some of them seemingly don't know P2.
    Elektor is saying, P2 would have 16 cores:
    https://www.elektormagazine.de/news/amd-schlagt-zuruck-die-zukunft-von-silizium

  • evanhevanh Posts: 16,023
    edited 2021-03-19 04:15

    The PIOs will be little processors that can bit-bash the pins. Can only focus on one control pin at a time. They'll be more comparable to cogs, but obviously hugely nerf'd in comparison, than smartpins.

    EDIT: I guess the smartpins are also little processors as well. But they're mode specific hardware state machines, without loadable code.

    EDIT2: Chip, at one stage, entertained making the smartpins like small FPGAs. Where they contained a small group of configurable logic and flops that needed a complex configuration to form any particular mode. Chip dropped it, I think, because the number of synthesised gates required to support this was far greater than just having a selection of fixed modes.

    Incorporating such features is exactly why Intel and AMD have bought out the two biggest FPGA producers.

  • TubularTubular Posts: 4,705
    edited 2021-03-19 05:10

    Well, i can vouch that Damien sure knows about P2, and about Pico's PIOs,

    Somewhere around 35~40mins in he shows how the WS2812 PIO code compiles to just a handful of 32 bit longs, combined with some timing metadata.

  • evanhevanh Posts: 16,023

    Got a link?

  • cgraceycgracey Posts: 14,206

    Did Damien say he had been working on this Pico project for the last 8 months?

  • TubularTubular Posts: 4,705

    Yes, something like 8 months, I thought it was longer. Its in the video, somewhere.

    I don't think this Pico stuff is a threat to the P2, and in fact will help sell/justify the multi core + pin peripheral approach, bitbanged DVI, multicore MicroPython... it will float both boats.
    Also, P2 is a natural destination for people that have outgrown 32 instruction PIOs

  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514

    The idea for smart pins (satellite peripheral controllers) is as old as dirt. Back in the day (ca. 1975) they were called "channels" and were microprogrammed. There's so much prior art on the subject, I can't imagine how a new patent stands a chance.

    -Phil

  • TubularTubular Posts: 4,705

    At some stage the patent application will be be published, lets wait and see. It only takes that one, well-argued inventive step beyond prior art to get a patent.

    I was talking to the local supplier of those Pico's today, they are sold out for a month or so.

  • evanhevanh Posts: 16,023
    edited 2021-03-19 06:48

    Hmm, I don't see any video. Another forum issue I guess. Which post has it?

  • TubularTubular Posts: 4,705

    This is the link
    www.youtube.com/watch?v=MQTZFrBrwac

  • evanhevanh Posts: 16,023

    Thanks

  • ColeyColey Posts: 1,110

    One thing they did get bang on was the launch of the Pico.

    Projects using the Pico from day one guaranteed a lot of exposure, that coupled with the RPi Foundation's marketing team ;-)

    We just need to demonstrate that P2 is more powerful especially with the Micropython port to P2 (thanks to team Oz!) and get the word out....

  • evanhevanh Posts: 16,023
    edited 2021-03-19 09:54

    At 37:30, 8 to 10 months.

    Ouch! Damien said 32 instruction words per block. Two blocks, four PIOs per block.

  • evanhevanh Posts: 16,023
    edited 2021-03-19 11:02

    Ah, okay, the idea is each block has up to four state machines to manage an interface. And the IN and OUT instructions are arbitrary width, up to 32 bit wide, and arbitrary recurring cycles. IN/OUT is the real feature - They're running in their own state machines themselves. Everything else is just support.

    So, in some respects one block is like one smartpin. On the other hand, that block can manage wide buses which a smartpin by itself never can. A cog + smartpin + streamer comes to bear for this. But a cog can struggle on the timing requirements for some interfaces.

    I can see the attraction here. Effectively only two of them though.

  • evanhevanh Posts: 16,023

    Oh, neat, I think ... each PIO program can be extended indefinitely via streaming into OUTs ... maybe.

  • Cluso99Cluso99 Posts: 18,069

    The quick zoom clip was interesting ;)

    Interesting. RP2040 has 8 state machines and each one can control up to one pin, for a whopping total of 8 pins.
    You cannot do every frequency as the main clock only has some? divisors.
    Each state machine can generate an interrupt on a pin change, but not a group change/mask.
    There is a tiny fifo on each state machine. It can shift in or out a group of bits ie like the serial shifter in the smart pins.

  • evanhevanh Posts: 16,023
    edited 2021-03-19 11:49

    Cluso,
    The PIOs are way better than what Damien describes there. You'll notice he isn't confident to answer with anything more than that demo program for the PIO. Hardware workings clearly isn't his deep knowledge. I'm guessing he's been given assistance just to write that example. Totally different level of confidence when he answers questions on micro-python.

    PS: I've started reading the datasheet that Damien referred to a few times - https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf

  • yetiyeti Posts: 818

    They started to look at reïmplementing the RP2040's PIOs but probbbly I'm not completely uptodate.
     
    From my notes:
     
    (github) An attempt to recreate the RP2040 PIO in an FPGA
    (MyStorm) RP2040 PIO FPGA implementation
    (YT/Folknology) RP2040 and PIO model
    (YT/Folknology) RP2040 PIO Deep Dive with deconstruction for FPGA and learning
    (YT/Folknology) RP2040 PIO deconstruction part 3
    (YT/Folknology) RP2040 PIO deconstruction part 4
    (YT/Folknology) PIO part 5 implementing a Stepper motor driver

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