P2 ADC Redrawn Schematic

sjgallagher2

Hey all, I redrew the schematic posted by Chip here, keeping a lot of the detail but substituting a few things and removing the enable/disable support circuitry to make it easier to understand. There's also a version I did with the full schematic, but this version is neater and shows a bit more of the design intent vs. implementation.

I have some questions about how it all works though, if someone could direct me a bit. Here's what I understand so far.

The output is buffered from a D flip-flop fed by the inverter chain. This signal is fed back to transistors M1-M4 (in my schematic) which are driven by the precision currents iUP and iDN. Capacitors C1 and C2 are integrating caps. Transistors M1-M4 switch the path, with two cases: (1) iUP to LOD, BAL to iDN; and (2) iUP to BAL, iDN to LOD. Case 1 happens for bitstream=1, case 2 for bitstream=0. It seems like BAL is the integrating signal, and is obviously related closely to the input INFB, but I haven't sat down with the transistor circuit to figure out what it's doing yet. The LOD is tracking the integration voltage (BAL) to within a few mV according to Chip, I'm guessing the amplifiers are comparators and this works by feeding back the inverted output of the comparator, creating a sort of PCM circuit, which is filtered by the resistor and associated capacitors.

iUP is an independent precision current source, while iDN is related to the MID/RFB circuit; MID is connected to a voltage divider (1/2) of the voltage VIO-GIO (ideally VIO/2). However, I don't understand the role of RFB yet (RFB=resistor feedback?), and I don't understand how that circuit affects iDN. The INFB signal itself is used with the (possible) comparator to compare INFB and MID, and the output drives the BAL integrating signal as well as the INFB signal itself. A symmetric circuit compares RFB to MID, affecting iDN somehow, and also affecting BAL and INFB.

At the input, you have the pin pad (PA) and its even-odd counterpart (PB); the multiplying circuit is implemented by a selector circuit (represented here as a MUX) with scaled resistor values, and the selector circuit feeds the op-amp/comparator/what-have-you. I'm guessing the INFB signals coming from within the transistor circuits are current sinks/sources, because it wouldn't make sense for the op-amp/comparator/etc to use current inputs when MID is seemingly just a voltage to a high-impedance input. By using smaller resistor values, the same current generates smaller voltage drops across PA to INFB, but these currents must be pretty small (resistors are scaled to 530k).

I don't fully understand what's going on yet, I need to take a second and piece together those transistor current source circuits, but I think this is in the ballpark. Am I on the right track or am I confused?

--Edit--

By the way, I'm piecing together the blocks, but I still don't understand basic things like the inverter chain (according to Chip it makes the 0/1 decision), and most importantly, how this all fits together to make a delta-sigma (which I'm not too familiar with anyway...)

Tubular

Nice work its so great to see some attention on this

One thing, the PB signal into the MUX was causing some crosstalk issues and was cut (made open circuit) in the Rev C silicon

Tubular

There's a neat Sigma Delta simulator here, just click the 'next step' to see how the magic happens
https://www.analog.com/en/design-center/interactive-design-tools/sigma-delta-adc-tutorial.html#

I wonder whether Chip would be up for explaining the subtleties of this schematic in a zoom session? He has described some of the details before, like those M1-M4 fets are like tiny 'knife switches' that quickly cut where the currents flow to, being either the balance point or the active load, so that the current sources always see a similar load

ErNa

This type of ADC is best seen as a charge balancer. There are two current sources: on is voltage controlled (analog) and one is time controlled (digital). Both current sources feed a single capacitor. As long as both current in average are equal (and opposed), the capacitors voltage doesn't change. The analog I-source goes to the world, the digital I-source can be switched on and off. It now is counted how often the digital source has to inject charge to the cap to keep the cap voltage constant and so is the inverse of the analog input signal. The streamed output of the digital source is counted and filtered and represents the digital value of the analog input.