Clock/Crystal input
Circuitsoft
Posts: 1,166
in Propeller 2
Given a situation where precise timing is necessary, and a 10MHz reference signal is available, could that be AC coupled to XIN to provide precise timing of the chip?
The reference signal is usually 0.5-1.0Vpp, but 1Vrms isn't unusual either.
I imagine that the chip running at 10MHz off the reference would be extremely solid. If, however, I used the PLL to get to 180 or 200MHz, how precise would timing remain? What kinds of phase noise do the PLL provide?
Comments
The XI pin might receive that 10MHz if you capacitively coupled it and selected a crystal mode:
CON
_xtlfreq = 10_000_000
_clkfreq = 200_000_000
The only question is whether or not the amplitude is high enough from your source.
The PLL will run at the frequency you set, assuming the PLL can pick multipliers and dividers that work. The jitter is quite low.
Is that from the datasheet?
Maybe we can have a draft datasheet in the meantime? Some of us could do our own testing to determine the parameters and limits that we observe.
What is the required amplitude?
Probably nearly 1V.
This is in the works, actually. Pretty much like you're imagining.
So, may as well use a clock buffer like a PL133, as that's not much more expensive than an analog amplifier, and has built-in AC coupling.
An AC-coupled bipolar or mosfet single-transistor class A or AB amplifier with a gain of about 1.5-2 works OK at "low" frequencies in similar applications (10MHz is pretty low as far as such amplifiers go with the right transistors). I've used a 2N3904 equivalent and it worked thus far - it also acts as a low-pass filter that rejects harmonics. Not a power miser by any stretch of imagination - it runs as hot as I dare.
Probably a little logic buffer gate running off 1.2-1.8V would work as well, and consume an order of magnitude less energy
I'm using that with a 26MHz clipped sine 3.5x2mm oscillator typically used for GPS circuits and thus dirt cheap (under $1 in quantity). That one stays +/-2ppm in my application, under worst case operating conditions, and has very respectable phase noise too (they actually specify it in the datasheet, whereas most CMOS/TTL oscillators specify jitter only if they are magnanimous, but are usually mum about such important things...).
These oscillators seem to ebb and flow price- and availability-wise over time, so occasionally it has to be changed to something else to keep the price advantage. Thankfully my application is not particular sensitive to what exact clock I run it at, as long as it's known, so I usually go with whatever is the cheapest at the time. That clock only drives the PLL and is essentially undetectable in EMC tests (in my application, YMMV), so changing it a few MHz up or down doesn't matter in this case.
That doesn't work for HDMI usually, where the entire clock scheme has to be designed around the desired pixel clock. It does work for DisplayPort, though, since that one decouples transport rate from pixel rate, but is a bit of a pain to work with - the external interface chip has its own "binary blob" firmware that you have to load into it, to handle the AUX datastream that DP needs to set things up. At least you don't need to write your own DP AUX protocol support on the P2 side - that one is basically a high-level engineering "masturbation", totally pointless as an exercise when all you want is push some pixel bits around.
Yes, 10 MHz will be fine.
I’ve tested clipped sine, AC coupled to 38.4MHz which has gain above 1, and 48 MHz works but is more marginal, with gain close to unity.
Is the crystal oscillator basically a Schmitt Trigger inverter? Could the 10MHz input be driven via a capacitor with a resistor to feed-back?
Seems the minimum signal level that I could want to work on would be 0.6vP-P, so if I built an RC Oscillator ~7MHz, but fed the 10MHz signal into the bottom of the cap, then it would be a solid 10MHz input.
No, it is an unbuffered inverter amplifier
Yes, tho the resistor is already included, so a series cap is all that is needed.
I tested Clipped Sine drive into P2 XI and that worked fine to a 38.4MHz test point.
26MHz has measurably more gain, and 38.4MHz is about the practical max.
A 10MHz clipped sine drive (0.8vp-p min) should be fine.
Phase noise you would need to measure.
On display type uses, the jitter becomes visible as PFD drops, and PFD below 1MHz is usually best avoided.
On the general topic of MCU PLL phase noise and phase effects, I also saw this thread about ST's PLLs :
https://www.eevblog.com/forum/microcontrollers/timing-stability-of-mcu-plls/
which links to
https://www.jaybee.cz/software/stm32-hse-oscillator-stability-problem/
I don't think P2 has that effect, and it is not easy to imagine what could cause such slow sawtooth-phase-walking. Fractions of ppm over many seconds ?
Last I heard, XI is a logic buffer input, non-Schmitt. There was some discussion about glitches getting into the crystal loop from nearby toggling pins. Chip's estimated 1.0 V requirement will be to avoid such occurrences.
I'm a little tempted to get the Eval Board, swap out the crystal for a 10MHz 8pf (RH100-10.000-8-2020 or similar), and put a 10pF cap between Xi and the 10MHz input. Would that reliably lock?
Interesting experiment. I'm not sure 'lock' is quite the correct term.
I guess a typical power up could see the Xtal start oscillating << 1ms, and then the RefIn may enable some time later, so maybe you could call that hand-over time a 'lock' ?
With active RefIn the crystal would work more as a narrow band filter - you should be safely clear of the series resonant point, and close to the normal parallel resonant point.
The P2 PLL clock is taken from a double buffer connected to XI, and not XO, so you would need to experiment to see if a crystal made any measurable difference.
P2 also lacks independent control of Ci and Co, so picking the effective CL of 3 C's could need some testing.
Also note with a crystal fitted, if your cable fell off, the P2 would still operate - that may be a plus or a minus, depending on what matters to you
Some Xtal Graphs are here
https://electronics.stackexchange.com/questions/413054/confusing-quartz-crystal-impedance-graphs
The worst outcome would be a combination that was unsure if it should follow Xtal or RefIn, and bounced between the two choices
Reducing the coupling cap, and enable/disable of RefIn, to verify hand-over still occurred, could indicate what margin you have from that zone.
The next edge board is coming with a precision oscillator. Maybe copy that?
Yes, I think that uses a 2GU04 to buffer clipped sine to rail-rail at P2, so makes it more tolerant of P2 pin / layout crosstalk, by keeping the 'analog bits' clear of P2.