P2 Electrical Characteristics?

n_ermosh

Do we have anything like an electrical datasheet for P2 yet? even a work in progress with basic info like required Vdd/Vio current, min/max Vdd/Vio voltages, maximum current out of a pin, etc etc? I'm designing a PCBA with a P2 and realizing I can't find any of this info. If nothing like this has been written yet, does anyone have that info readily available? Realistically, I just need the following for designing the power tree:

- Vdd min/max current (@1.8V)
- Vio min/max current (@3.3V)
- Vdd max voltage
- Vio max voltage

evanh

Same from a few weeks back - https://forums.parallax.com/discussion/172610/p2-full-datasheet-badly-wanted-and-needed/p1

Some questions have been asked in the past too. JMG has requested some specific AC characteristics.

The max voltages are typical affairs. Chip was originally wanting to give VIO a large headroom but had to settle for something lower due to an unexpected latch-up potential. I've forgotten the exact voltages.

Minimum current isn't likely to be a useful number. IDD lowest will be with RCSLOW clock and all cogs waiting. IIO lowest will be with all pins unused.

Maximum currents is relatively high, but not a very practical number. There is just so many circuits that don't get used together. That said, making torture test program and pushing to 360 MHz sysclock, I've got to about 1.9 amps on VDD rail. I haven't tried any VIO testing.

Tubular

n_ermosh wrote: »

Do we have anything like an electrical datasheet for P2 yet? even a work in progress with basic info like required Vdd/Vio current, min/max Vdd/Vio voltages, maximum current out of a pin, etc etc? I'm designing a PCBA with a P2 and realizing I can't find any of this info. If nothing like this has been written yet, does anyone have that info readily available? Realistically, I just need the following for designing the power tree:

- Vdd min/max current (@1.8V)
- Vio min/max current (@3.3V)
- Vdd max voltage
- Vio max voltage

These aren't official but here's what we've found
- Vdd min/max current (@1.8V) 34uA / 2A
- Vio min/max current (@3.3V) min current is almost nothing, or about 1mA for each ADC enabled. But max could be 2A (64 pins driving 30mA each)
- Vdd max voltage I'd stick to +10% on both of these max voltages
- Vio max voltage

The other thing to note is the PLL gets it supply from VIO2831, so you want that pin quiet for lowest jitter (but it works ok even without special attention)

evanh

Tubular wrote: »

The other thing to note is the PLL gets it supply from VIO2831, so you want that pin quiet for lowest jitter (but it works ok even without special attention)

One thing that has happened to more than one person already: A damaged I/O pin in that group can short it out and that bricks the whole prop2 because RCFAST oscillator then has no power.

evanh

Found one of JMG's more recent requests - https://forums.parallax.com/discussion/comment/1490594/#Comment_1490594

Here's some testing - https://forums.parallax.com/discussion/comment/1482530/#Comment_1482530

n_ermosh

Thanks for the info everyone!

Min current can be useful for designing switching regulators, so was curious if anyone had that number.

Tubular wrote: »

The other thing to note is the PLL gets it supply from VIO2831, so you want that pin quiet for lowest jitter (but it works ok even without special attention)

This should be rather loudly documented. I'm sure it would lead to a lot of headaches...

CJMJ

@Tubular Would it be a good rule to avoid using pins 28-31 until [absolutely] necessary?

Tubular

I'd hate to see something like that become a 'rule'. Its really just one of those facts for the obsessive, nothing to get worried about.
The kind of use cases where it might matter are combinations of pushing high frequencies and where jitter needs to be minimised. Heck for us to notice anything we were driving 2000x1500 video into a special VGA monitor on the rev A chips. Chip then improved things for the rev B / rev C chips