forcing a pin low
ManAtWork
Posts: 2,176
in Propeller 2
For my motion control projects I need some sort of emergency shutdown. I have an enable pin that enables the power stages for the motors when high and cuts all currents when low.
Unfortunatelly, the propeller has the OUT and DIR signals of all pins driven by a large OR gate. So if any of the other cogs accidentally drives DIR and OUT of that pin high (by means of a software bug) it overrides driving it low. This would be just a false state in most applications but in my case it could burn expensive equipment.
On the P1 I solved this with an external flipflop that can be set only with a falling edge of a pin and is cleared by the alarm condition. But external circuits cost money and board space and I think the P2 can do better.
What about configuring the pin as smart pin constantly driving out low, for example as PWM output with Y=0. Of course, the smart pin mode and XY registers and DIR (reset) can still be overwritten by other cogs but if I do wrpin in an endless loop it should be pretty bullet proof. A cog running totally amok could cogstop the safety guard cog but that's very unlikely if no on-the-fly updates are made and no memory corruption occurs.
The P2 has no brown out circuit if IO remember correctly. But my voltage regulator has a "power good" signal driving reset.
Any objections or ideas for improvement?
Unfortunatelly, the propeller has the OUT and DIR signals of all pins driven by a large OR gate. So if any of the other cogs accidentally drives DIR and OUT of that pin high (by means of a software bug) it overrides driving it low. This would be just a false state in most applications but in my case it could burn expensive equipment.
On the P1 I solved this with an external flipflop that can be set only with a falling edge of a pin and is cleared by the alarm condition. But external circuits cost money and board space and I think the P2 can do better.
What about configuring the pin as smart pin constantly driving out low, for example as PWM output with Y=0. Of course, the smart pin mode and XY registers and DIR (reset) can still be overwritten by other cogs but if I do wrpin in an endless loop it should be pretty bullet proof. A cog running totally amok could cogstop the safety guard cog but that's very unlikely if no on-the-fly updates are made and no memory corruption occurs.
The P2 has no brown out circuit if IO remember correctly. But my voltage regulator has a "power good" signal driving reset.
Any objections or ideas for improvement?
Comments
I was thinking inverting the output (using CIO bits) could also help in that any other cog drvh's would cause a '0' to be output, but you still have the problem an errant wrpin could undo that protection
I guess that would mean any cog could make it 0 instead of 1. Would that help?
I might take the cpu out of the equation and use relays for the safety mechanisms...