P2 running FPGA code on P2 Edge

ti85

Quick question about VGA example from FPGA boards…see code below:





'******************************
'* VGA 640 x 480 x 8bpp-lut *
'******************************

CON

intensity = 80 '0..128

fclk = 80_000_000.0
fpix = 25_000_000.0
fset = (fpix / fclk * 2.0) * float($4000_0000)

vsync = 0 'vsync pin (all FPGA boards now)

DAT org
'
'
' Setup
'
hubset #$FF 'set clock to 80MHz

rdfast #0,##$1000-$400 'load .bmp palette into lut
rep @.end,#$100
rflong y
shl y,#8
wrlut y,x
add x,#1
.end
rdfast ##640*480/64,##$1000 'set rdfast to wrap on bitmap

setxfrq ##round(fset) 'set transfer frequency to 25MHz

'the next 4 lines may be commented out to bypass level scaling

setcy ##intensity << 24 'r set colorspace for rgb
setci ##intensity << 16 'g
setcq ##intensity << 08 'b
setcmod #%01_0_000_0 'enable colorspace conversion

wrpin dacmode,#3<<6 + 0 'enable dac modes in pins 0..3
'
'
' Field loop
'
field mov x,#33 'top blanks
call #blank

mov x,#480 'set visible lines
line call #hsync 'do horizontal sync
xcont m_rf,#0 'visible line
djnz x,#line 'another line?

mov x,#10 'bottom blanks
call #blank

drvnot #vsync 'sync on

mov x,#2 'sync blanks
call #blank

drvnot #vsync 'sync off

jmp #field 'loop
'
'
' Subroutines
'
blank call #hsync 'blank lines
xcont m_vi,#0
_ret_ djnz x,#blank

hsync xcont m_bs,#0 'horizontal sync
xcont m_sn,#1
_ret_ xcont m_bv,#0
'
'
' Initialized data
'
dacmode long %0000_0000_000_1010000000000_01_00000_0

m_bs long $7F010000+16 'before sync
m_sn long $7F010000+96 'sync
m_bv long $7F010000+48 'before visible
m_vi long $7F010000+640 'visible

m_rf long $7F080000+640 'visible rlong 8bpp lut

x res 1
y res 1
'
'
' Bitmap
'
orgh $1000 - $436 'justify pixels at $1000, pallete at $1000-$400
file "bitmap2.bmp" '640 x 480, 8pbb-lut


If this code is ran on the P2 Edge…what are the pins assignments?

I think it’s pins 0 through 4, but I’m not sure what pins are R,G,B,H, and V

Rayman

I don't think the Edge module has a VGA port, does it?
Maybe whatever you are plugging it into has one?

Anyway, VGA RGB&Hsync have to be on consecutive pins starting from a multiple of 4. HSync comes first.
VSync can be on any pin...

Publison

P2 Edge Mini breakout board and the Jon Mac board both have breakout pins for the A/V board from the Accessory Kit.

Cluso99

There are VGA examples for P2 in the pnut download. Haven’t looked but likely with PropTool 2.4 and later.

ozpropdev

The FPGA code will not run on the edge board without a few changeds,

The streamer modes changed from Rev A(FPGA) to Rev B/C silicon.
Also the HUBSET value nedds changing too.

ti85

Thank you for the help. I’ve now got the pin mapping figured out, but the change needed for the streamer is going to be a real challenge. I’ve never worked with smart pins before and the P2 has a lot of setup variations. Is there a P2 edge vga example that displays a bitmap graphic? All the examples I’ve found so far seem to be text type graphics

evanh

Interesting, I'd not noticed those examples had vanished from newer Pnut downloads.

FPGA/Pnut v33 is for the RevB silicon. Those ones should have correct streamer modes. Only thing to fix up is the HUBSET mode to get matching 80 MHz in finished silicon.

PS: I've attached example from v33k.

Rayman

There really should be a simple VGA example that works...

Rayman

Seems we lost these simple examples...
Couldn't find any that work with new Prop Tool...
So, remade them here:
http://forums.parallax.com/discussion/172624/simple-vga-wvga-spin2-examples