sawtooth vs. triangle PWM mode

ManAtWork

I just saw that in triangle PWM mode the Y register is sampled only every second frame period (once per count up/down cycle). This is a major design flaw as it unneccessarily either limits bandwidth or increases switching losses. For example, if the base period is 1 clock cycle and the frame period is 8000 then the PWM frequency at 160MHz system clock is 10kHz. The comparator is updated 10,000 times per second. So if I need 20,000 updates per second to reach the desired bandwidth I have to double the PWM frequency.

This is no problem for small transistors but for high power IGBT stages switching losses are typically in the same range as conductive losses. So doubling the PWM frequency also doubles switching losses and therefore requires a 50% oversized heatsink. This costs money and energy and has to be avoided.

So I think a possible workaround is to implement the triangle mode in software by using sawtooth mode instead and inverting output and Y value for every odd/even cycle.

ManAtWork

Hmm, this is not as easy as it seemed. I have to flip polarity of the output exactly at the same time when the negated Y value is captured at the end of a PWM counter frame. So it's not possible to wait on the IN event. Then the polarity inversion would happen a few cycles after the Y capture and that would cause a glitch. I think it's also difficult to predict the exact capture moment because the signal from the PWM comperator is pipelined through some flipflops before it reaches the low level pin control block.

I also can't stop the PWM counter by resetting the smart pin. This would add some cycles of delay before the next frame starts and that would ruin synchronisation between PWM and ADCs.

Is it possible to override the output state with the low level control? I saw there is an alternate source "OTHER" for the output driver but I don't understand if it comes from the OUTA/B source or the smartpin output. (Edit: The smart pin schematics shows shows RND as source for even pins and the negated even pin as source for odd pins "other")

A possible workaround would be to disable the output (change the low level control to floating) before the PWM Y capture, change the output polarity after it and finally re-enable the output. If it's only for a few clock cycles the capacity of the pin and PCB traces should help keeping the last state until the output is valid again.