Theoretical and usable Smart pin frequencies
PropGuy2
Posts: 360
in Propeller 2
I was experimenting with some NCO and sawtooth Smart pin commands to see what the usable frequency range might be.
So far I have tried: pinSTART(pp, P_OE | P_NCO_FREQ, x, 0 - and - pinSTART(pp, P_OE | P_PWM_SAWTOOTH, x, 0 )
then using the in-line PASM examples of Jon McPhalen and others with no problems.
The best output frequency I have so far is about 20 MHz Is this typical or am I missing something.? It seems low compared to the P1 "Synth" object code I was using ( however bad )
What would be the theoretical upper limit - and best usable (low jitter and low phase shift) frequencies I could expect with a Smart pin?
So far I have tried: pinSTART(pp, P_OE | P_NCO_FREQ, x, 0 - and - pinSTART(pp, P_OE | P_PWM_SAWTOOTH, x, 0 )
then using the in-line PASM examples of Jon McPhalen and others with no problems.
The best output frequency I have so far is about 20 MHz Is this typical or am I missing something.? It seems low compared to the P1 "Synth" object code I was using ( however bad )
What would be the theoretical upper limit - and best usable (low jitter and low phase shift) frequencies I could expect with a Smart pin?
Comments
For PWM mode there is no jitter, sysclock gets divided by the value in x. You can also go up to 1/2 sysclock, but then the pulswidth will always be 50%. For 1/4 sysclock you can choose 25,50, 75%, and so on, the divider defines the resolution of the pulswidth.
Andy
Try this:
The NCO and PWM modes are adders or dividers from SysCLK.
That means the highest PWM Freq is usually SysCLK/2 and SysCLK/N is possible, and the duty cycle can vary, but for odd divisions cannot be exactly 50%.
ie for /5 you can have 2 clocks low and 3 clocks hi, or 3 clocks low, and 2 clocks hi, whilst the 50% ideal would need an impossible 2.5 clocks hi and low.
NCO is generated by an adder, and for binary addition values, there is no jitter and SysCLK/2^N is possible.
For non binary addition values, you will always have jitter of SysCLK as the average frequency is correct, but it is being generated SysCLK quantized.
ie For a 200MHz P2 sysclk, 100MHz should be able to be generated by the HW.
This is one of the points where the P2 is actually a bit inferior to the P1. There is only one PLL for the main clock and none in the smart pins. With NCO mode you have a fairly high resolution for frequency. But that is only the "average" frequency. As the output can change only at the edges of the main system clock there is a lot of jitter for all frequencies that are not dividable from the sysclock by a whole number.
However, if you desperately need a PLL you can build one with only two external RC circuits and two open collector pins.
How does it work? Sounds interesting.
The classic 4046 PLL gives a template, of a two open collector design, for a 50% duty cycle out.
On P2 you could shave that a little with a schmitt sawtooth and a resistor feed from a DAC pin, so 2 pins on a P2 should manage this : one DAC, one self OSC pin and one cap, two resistors. (or two osc pins if you want 50% duty cycle)
Phase detector could be an external XOR, or maybe P2 pins can do that too ?
I have build this around 1990 to make a "flicker fixer" for the Amiga. I needed a pixel clock of ~28MHz but at the external video port there was only the color burst frequency (~3.5MHz) available. I used one of the early Xilinx FPGA which haven't got a real PLL. I have used a schematic like in the attached picture.
The actual oscillator is formed by R2+C2 and a feedback. T1 is part of an open drain output of the FPGA. I only showed it in the schematic for clarity. R2 feeds current into C2 so that the voltage at Osc slopes up. When the threshold of the FPGA input is reached C2 is discharged by T1.
The frequency is set by the current through R2 and therefore by the voltage of C1. Trim is connected to a tri-state output which is controlled by the phase comperator. Most of the time it's tri-stated. But if the Osc frequency is higher than the reference frequency (edge arrives earlier) then C1 is discharged a bit by a short low pulse. If the Osc frequency is lower (reference edge arrives earlier) then C1 is charged by a short high pulse.
At startup there is no oscillation so the reference edges always arrive earlier and C1 is constantly charged until the voltage is above the threshold and the oscillator starts working.
I don't know if and how this could be implemented with the P2 but I'm almost sure you, Chip, will find a way.
Ah, bad idea... if the feedback is synchronous to the P2 sysclock we have that jitter, again, which was the main reason to avoid NCO mode and build a PLL instead.
So we need some asynchronous feedback. But the pulse has to be long enough so that C2 is fully discharged, ... at least well below the threshold.
A simple inverted schmitt trigger with open drain output would do if the hysteresis is somewhat well defined (as it influences the frequency). Small variations of the hysteresis are compensated by the PLL loop. But a 74HC14 for example has a 1:3 range spec and that would probably throw the frequency out of the locking range. The P2 has schmitt triggers in the smart pins. What are ste specs for the hysteresis?